MT36LSDT12872G-13ED2 Micron Technology Inc, MT36LSDT12872G-13ED2 Datasheet - Page 19

• Manufacturer Part Number: MT36LSDT12872G-13ED2
• Description: MODULE SDRAM 1GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDT12872G-13ED2

• Memory Type: SDRAM
• Memory Size: 1GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured at 1.5V with equivalent load:
test biased at 1.4V.
with minimum cycle time and the outputs open.
operation over the full temperature range is ensured; (0°C ≤ T
commands, before proper device operation is ensured. (V
ered up simultaneously. Vss and V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sit between V
Q
t
a reference to V
High-Z.
level of 1.5V. If the input transition time is longer than 1ns, then the timing is mea-
sured from V
always be referenced to crossover. Refer to Micron Technical Note TN-48-09.
are otherwise at valid V
cycle rate.
mum cycle rate.
timing parameter.
frequency alteration for the test condition.
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
is dependent on output loading and cycle rates. Specified values are obtained
specifications are tested after the device is properly initialized.
DD
current will increase or decrease proportionally according to the amount of
t
50pF
CK = 7.5ns for -133 and -13E.
IL
IH
(MAX) and V
OH
DD
and V
or V
tests have V
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
IL
OL
IH
(or between V
. The last valid data element will meet
or V
t
19
SS
T = 1ns.
IH
t
t
t
DD
.
CKS; clock(s) specified as a reference only at minimum
WR +
WR.
IL
(MIN) and no longer at the 1.5V midpoint. CLK should
IL
= V
levels.
= 0V and V
SS
t
DD
RP; clock(s) specified as a reference only at mini-
Q must be at same potential.) The two AUTO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
Q = +3.3V ±0.3V; f = 1 MHz, T
and V
IH
IH
= 3.0V, using a measurement reference
) in a monotonic manner.
DD
©2002 Micron Technology, Inc. All rights reserved.
and V
A
≤ 55°C).
t
OH before going
t
REF refresh require-
A
DD
= 25°C; pin under
Q must be pow-
Notes