MT4HTF6464AY-53EA1 Micron Technology Inc, MT4HTF6464AY-53EA1 Datasheet - Page 7
![MODULE SDRAM DDR2 512MB 240DIMM](/photos/7/83/78383/mfg557-240-dimm_sml.jpg)
MT4HTF6464AY-53EA1
Manufacturer Part Number
MT4HTF6464AY-53EA1
Description
MODULE SDRAM DDR2 512MB 240DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT4HTF1664AY-40EB1.pdf
(19 pages)
Specifications of MT4HTF6464AY-53EA1
Memory Type
DDR2 SDRAM
Memory Size
512MB
Speed
533MT/s
Package / Case
240-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
General Description
Serial Presence-Detect EEPROM Operation
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-
mitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
(WP) is connected to V
2
C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
SS
, permanently disabling hardware write protection.
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
General Description
© 2003 Micron Technology, Inc. All rights reserved.