MT4LSDT864AG-13EG2 Micron Technology Inc, MT4LSDT864AG-13EG2 Datasheet
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MT4LSDT864AG-13EG2
Specifications of MT4LSDT864AG-13EG2
Related parts for MT4LSDT864AG-13EG2
MT4LSDT864AG-13EG2 Summary of contents
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SDRAM Unbuffered DIMM (UDIMM) MT4LSDT464A – 32MB MT4LSDT864A(I) – 64MB MT4LSDT1664A(I) – 128MB For component data sheets, refer to Micron’s Web site: Features • 168-pin, dual in-line memory module (DIMM) • PC100- and PC133-compliant • Unbuffered 2 • 32MB (4 ...
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... MT4LSDT464AG-133_ 2 MT4LSDT464AY-133_ 2 MT4LSDT464AG-10E_ 1 MT4LSDT464AY-10E_ 1 MT4LSDT864AG-13E_ MT4LSDT864AY-13E_ 1 MT4LSDT864AIG-133_ 1 MT4LSDT864AG-133_ 1 MT4LSDT864AIY-133_ MT4LSDT864AY-133_ 2 MT4LSDT864AG-10E_ 1 MT4LSDT864AY-10E_ MT4LSDT1664AG-13E_ MT4LSDT1664AY-13E_ 1 MT4LSDT1664AIG-133_ MT4LSDT1664AG-133_ 1 MT4LSDT1664AIY-133_ MT4LSDT1664AY-133_ 2 MT4LSDT1664AG-10E_ 2 MT4LSDT1664AY-10E_ Notes: 1. Contact Micron for product availability. 2. Not recommended for new designs. 3. The designators for component and PCB revision are the last two characters of each part number ...
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... DNU 42 CK0 63 Notes: 1. Pin 126 is NC for 32MB and 64MB modules, or A12 for the 128MB module. Figure 2: Pin Locations (168-Pin DIMM) Front View PIN 1 Back View PIN 168 PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3 SD4C4_8_16X64AG.fm - Rev. D 1/07 EN 32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM ...
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Table 5: Pin Descriptions Pins may not correlate with symbols; refer to Table 4 on page 3 for more information Pin Numbers Symbol 27, 111, 115 RAS#, CAS#, WE# 42, 79 CK0, CK2 128 CKE0 30, 45 S0#, S2# 28, ...
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... Supply Power supply: +3.3V ±0.3V. Supply Ground. – Do not use: These pins are not used on these modules, but are assigned pins on other modules in this product family. – Not connected: These pins are not connected on these modules. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... BA0–BA1 Notes: 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide found on Micron’s Web site: www.micron.com/support. 3. Standard modules use the following SDRAM devices: MT48LC4M16A2TG(IT) (32MB); ...
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... A0–A8 for 64MB and 128MB) are used to select the starting device column location for the burst access. These modules provide for programmable READ or WRITE burst lengths locations, or the full page with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
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SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP . Starting at some point during this 100µs period ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by ...
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... Figure 4: Mode Register Definition Diagram 32MB and 64MB Modules 128MB Module Notes: 1. M11 and M10 should be programmed = “0, 0” to ensure compatibility with future devices. 2. M12, M11, and M10 should be programmed = “0, 0, 0” to ensure compatibility with future devices. PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3 SD4C4_8_16X64AG ...
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Table 6: Burst Definition Table Burst Length Starting Column Address Full page ( A0–Ai (location Notes: 1. For full-page accesses 256 (32MB ...
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Figure 5: CAS Latency Diagram CLK COMMAND DQ CLK COMMAND DQ CAS Latency (CL the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency ...
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Table 7: CAS Latency Table Speed -13E -133 -10E PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3 SD4C4_8_16X64AG.fm - Rev. D 1/07 EN 32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM Allowable Operating Clock Frequency (MHz ≤133 ≤100 ≤100 Micron Technology, Inc., ...
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Commands This truth table provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 64Mb, 128Mb, or 256Mb SDRAM component data sheet. Table 8: Truth Table – Commands and DQMB Operation ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
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Table 11: AC Functional Characteristics (Continued) Notes 11, 31; notes appear on page 20 Parameter Data-out to high-impedance from PRECHARGE command Table 12: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, ...
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Table 13: DC Electrical Characteristics and Operating Conditions Notes notes appear on page 20; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Input leakage current: Any input ...
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I Specifications DD Table 14: I Specifications and Conditions – 32MB DD Notes 11, 13; notes appear on page 20; V Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE ...
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Table 16: I Specifications and Conditions – 128MB (Continued) DD Notes 11, 13; notes appear on page 20; V Parameter/Condition Auto refresh current: CS# = HIGH; CKE = HIGH Self refresh current: CKE ≤ 0.2V PDF: 09005aef8078bc7c/Source: ...
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Notes 1. All voltages referenced This parameter is sampled MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications ...
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... SR) 168-Pin SDRAM UDIMM t WR and PRECHARGE commands). CKE may be used 7.5ns; for -133 and t RAS used in -13E speed grade modules is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 21 Notes t RP) begins 7ns for -13E; ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions, as indicated in Figure 6 on page ...
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Figure 7: Definition of Start and Stop SCL SDA Figure 8: Acknowledge Response from Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Table 17: EEPROM Device Select Code The most significant bit (b7) is sent first ...
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Figure 9: SPD EEPROM Timing Diagram SCL t SU:STA SDA IN SDA OUT Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic ...
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Table 20: Serial Presence-Detect EEPROM AC Operating Conditions (Continued) Notes appear below; All voltages referenced to V Parameter/Condition WRITE cycle time Notes avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and ...
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Table 21: Serial Presence-Detect Matrix “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW.” Byte Description 0 Number of bytes used by Micron 1 Total number of SPD memory bytes 2 Memory type 3 Number of row addresses 4 Number of ...
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Table 21: Serial Presence-Detect Matrix (Continued) “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW.” Byte Description 33 Command and address hold time 34 Data Signal input setup time 35 Data signal input hold time 36–61 Reserved 41 Device minimum active/auto-refresh ...
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Module Dimensions Figure 10: 168-Pin DIMM 2.00 (0.079) R (2X) U1 3.00 (0.118) (2X) 3.00 (0.118) TYP 3.00 (0.118) TYP 66.68 (2.625) PIN 1 (PIN 85 ON BACKSIDE) Notes: 1. All dimensions in millimeters (inches); MAX/MIN or typical (TYP) where ...