MT18HTF25672DY-40ED1 Micron Technology Inc, MT18HTF25672DY-40ED1 Datasheet
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MT18HTF25672DY-40ED1
Specifications of MT18HTF25672DY-40ED1
Related parts for MT18HTF25672DY-40ED1
MT18HTF25672DY-40ED1 Summary of contents
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DDR2 SDRAM Registered DIMM (RDIMM) MT18HTF6472(P)D – 512MB MT18HTF12872(P)D – 1GB MT18HTF25672(P)D – 2GB For component data sheets, refer to Micron’s Web site: Features • 240-pin, registered dual in-line memory module • Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or ...
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... Part Numbers and Timing Parameters – 1GB Modules Base device: MT47H64M8 Module 2 Part Number Density MT18HTF12872(P)DY-80E__ MT18HTF12872(P)DY-800__ MT18HTF12872(P)DY-667__ MT18HTF12872(P)DY-53E__ MT18HTF12872(P)DY-40E__ Table 5: Part Numbers and Timing Parameters – 2GB Modules Notes appear below; base device: MT47H128M8 Module 2 Part Number Density MT18HTF25672(P)DY-80E__ MT18HTF25672(P)DY-800__ MT18HTF25672(P)DY-667__ MT18HTF25672(P)DY-53E__ MT18HTF25672(P)DY-40E__ Notes: 1. Data sheets for the base devices can be found on Micron’ ...
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Pin Assignments and Descriptions Table 6: Pin Assignments 240-Pin RDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin DQ19 61 REF ...
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Table 7: Pin Descriptions Symbol Type ODT0, ODT1 Input On-die termination: ODT (registered HIGH) enables termination resistance internal to (SSTL_18) the DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and CB. The ODT ...
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Functional Block Diagram Figure 2: Functional Block Diagram RS1# RS0# DQS0 DQS0# DM0/DQS9 NC/DQS9# DM/ NU/ CS# DQS DQS# RDQS RDQS# DQ DQ0 DQ DQ1 DQ DQ2 DQ DQ3 DQ DQ4 DQ DQ5 DQ DQ6 DQ DQ7 DQS1 DQS1# DM1/DQS10 ...
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... READs and by the memory controller during WRITEs. DQS is edge- aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. ...
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... Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’ ...
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I Specifications DD Table 10: DDR2 I Specifications and Conditions – 512MB DD Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition Operating one bank ...
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Table 11: DDR2 I Specifications and Conditions – 1GB DD Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter/Condition Operating one bank active-precharge current: t ...
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Table 12: DDR2 I Specifications and Conditions (Die Revision A) – 2GB DD Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet Parameter/Condition Operating one bank ...
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Table 13: DDR2 I Specifications and Conditions (Die Revision E) – 2GB DD Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet Parameter/Condition Operating one bank ...
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Register and PLL Specifications Table 14: Register Specifications SSTU32866 devices or equivalent JESD82-16 Parameter Symbol high-level IH DC input voltage DC low-level input voltage AC high-level ...
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Table 15: PLL Specifications CU877 device or equivalent JESD82-8.01 Parameter Symbol DC high-level input voltage V DC low-level input voltage V V Input voltage (limits high-level input voltage DC low-level input voltage V Input differential-pair cross V voltage ...
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Serial Presence-Detect Table 17: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input ...
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Table 19: Serial Presence-Detect Matrix Byte Description 0 Number of SPD bytes used by Micron 1 Total number of bytes in SPD device 2 Fundamental memory type 3 Number of row addresses on SDRAM 4 Number of column addresses on ...
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Table 19: Serial Presence-Detect Matrix (continued) Byte Description 27 MIN row precharge time, 28 MIN row active-to-row active, 29 MIN RAS#-to-CAS# delay, 30 MIN active-to-precharge time, 31 Module rank density 32 Address and command setup time, 33 Address and command ...
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Table 19: Serial Presence-Detect Matrix (continued) Byte Description 47–61 Optional features, not supported 62 SPD revision 63 Checksum for bytes 0–62 ECC/ECC and parity 64 Manufacturer’s JEDEC ID code 65–71 Manufacturer’s JEDEC ID code 72 Manufacturing location 73–90 Module part ...
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Module Dimensions Figure 3: 240-Pin DDR2 DIMM 2.00 (0.079) R (4X 2.50 (0.098) D (2X) 2.30 (0.091) TYP PIN 1 2.21 (0.087) TYP 1.0 (0.039) 1.0 (0.039) TYP TYP U13 U14 U15 3.05 (0.120) TYP PIN 240 ...