MT36HTJ51272Y-40ED2 Micron Technology Inc, MT36HTJ51272Y-40ED2 Datasheet - Page 11
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MT36HTJ51272Y-40ED2
Manufacturer Part Number
MT36HTJ51272Y-40ED2
Description
MODULE DDR2 4GB 240-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT36HTJ51272Y-40EA2.pdf
(14 pages)
Specifications of MT36HTJ51272Y-40ED2
Memory Type
DDR2 SDRAM
Memory Size
4GB
Speed
400MT/s
Package / Case
240-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 13:
PDF: 09005aef822553c2/Source: 09005aef822553af
HT36HTJ51272.fm - Rev. B 7/06 EN
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to the pull-up
resistor, and the EEPROM does not respond to its slave address.
SS
; V
DDSPD
= +1.7V to +3.6V
4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
11
t
WRC) is the time from a valid STOP condition of a write
t
Symbol
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
t
R
F
I
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
–
–
–
–
–
Serial Presence-Detect
Max
300
400
0.3
0.9
50
10
©2003 Micron Technology, Inc. All rights reserved.
–
–
–
–
–
–
–
–
–
Units
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Notes
1
2
2
3
4