MT18VDVF12872Y-40BF1 Micron Technology Inc, MT18VDVF12872Y-40BF1 Datasheet - Page 11
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MT18VDVF12872Y-40BF1
Manufacturer Part Number
MT18VDVF12872Y-40BF1
Description
MODULE DDR 1GB 184-DIMM VLP
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDVF12872G-40BD4.pdf
(12 pages)
Specifications of MT18VDVF12872Y-40BF1
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Operating Current
3.51A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Serial Presence-Detect
Table 12:
Table 13:
Serial Presence-Detect Data
PDF: 09005aef81c7380b/Source: 09005aef81c7380e
DVF18C_128x72.fm - Rev. C 11/07 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current: SCL = SDA = V
Power supply current: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
Clock/data fall time
Clock/data rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
Serial Presence-Detect EEPROM AC Operating Conditions
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
DD
- 0.3V; All other inputs = V
DD
DD
11
SS
1GB (x72, ECC, SR): 184-Pin DDR VLP RDIMM
or V
DD
t
t
Symbol
t
t
t
t
WRC) is the time from a valid stop condition of a write
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SCL
AA
DH
t
t
t
R
F
I
Symbol
V
DDSPD
V
V
I
V
I
I
I
LO
CC
SB
OL
LI
IH
IL
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
–
–
–
–
–
V
DDSPD
Min
2.3
–1
–
–
–
–
–
Serial Presence-Detect
Max
300
300
400
0.9
× 0.7 V
50
10
–
–
–
–
–
–
–
–
–
©2005 Micron Technology, Inc. All rights reserved
V
DDSPD
DDSPD
Units
kHz
Max
ms
µs
µs
ns
ns
ns
µs
µs
µs
ns
µs
ns
µs
µs
3.6
0.4
2.0
10
10
30
+ 0.5
× 0.3
Notes
Units
1
2
2
3
4
mA
µA
µA
µA
V
V
V
V