MT36HTS51272FY-53EA2E3 Micron Technology Inc, MT36HTS51272FY-53EA2E3 Datasheet - Page 27

• Manufacturer Part Number: MT36HTS51272FY-53EA2E3
• Description: MODULE DDR2 4GB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS51272FY-53EA2E3

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 533MT/s
• Package / Case: 240-FBDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AMB Initialization
Figure 7:
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
AMB Initialization Flow Diagram
The FBDIMM initialization process generally follows the top-to-bottom sequence of
state transitions shown in Figure 7. The host must sequence the AMB devices through
the disable, calibrate, (back to disable), training, testing, and polling states to move the
AMBs into the active channel L0 state. The value in parentheses in each state bubble
indicates the condition/activity of the links during these states.
Each bit lane is initialized (mostly) independently to support fault tolerance. The transi-
tions in Figure 7 represent the transitions of the AMB core logic state machine and are
taken when the transition event is detected on the minimum required number of south-
bound bit lanes. The chain of FBDIMM links connecting the host to the AMBs must each
be initialized to establish the timing for broadcasting data frames in the southbound
direction and for merging data frames in the northbound direction. The AMBs on the
channel are generally initialized as a group, but because each AMB is individually
addressable, many alternate initialization sequences may be employed.
Testing (TS1)
Each bit lane is individually
tested.
Polling (TS2)
Communicates channel
capabilities of individual
AMB devices.
Config (TS3)
Communicates channel
width configuration to
AMB devices.
L0 (frames)
Active channel; frames of
information flow between
host and AMB devices.
Recalibrate (NOPs )
Channel idled to recalibrate
TX and Rx circuits.
Disable (EI)
Channel inactive, the inter-
face signals are in
low-power EI.
Training (TS0)
Initial bit alignment and
frame alignment training.
Power-up
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
27
Calibrate (1)
Low-latency, power-saving
condition. (optional)
L0s (EI)
Low-latency, power-saving
condition. (optional)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
AMB Initialization
Preliminary