MT36HTS51272FY-53EA3E3 Micron Technology Inc, MT36HTS51272FY-53EA3E3 Datasheet - Page 28
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MT36HTS51272FY-53EA3E3
Manufacturer Part Number
MT36HTS51272FY-53EA3E3
Description
MODULE DDR2 4GB 240FBDIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT36HTS51272FY-53EA2E3.pdf
(35 pages)
Specifications of MT36HTS51272FY-53EA3E3
Memory Type
DDR2 SDRAM
Memory Size
4GB
Speed
533MT/s
Package / Case
240-FBDIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Serial Presence-Detect
SPD Clock and Data Conventions
SPD Start Condition
SPD Stop Condition
SPD Acknowledge
PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions, as shown in Figures 8
and 9 on page 29.
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-
sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data, as shown in Figure 10 on page 29.
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each
subsequent eight-bit word. In the read mode, the SPD device will transmit eight bits of
data, release the SDA line, and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Serial Presence-Detect
©2006 Micron Technology, Inc. All rights reserved.
Preliminary