MT4VDDT1664HY-335F3 Micron Technology Inc, MT4VDDT1664HY-335F3 Datasheet - Page 9

• Manufacturer Part Number: MT4VDDT1664HY-335F3
• Description: MODULE DDR 128MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT1664HY-335F3

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 200MHz
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 16Mx64
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 880mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1344

Idd Specifications
Table 9:
PDF: 09005aef837131bb/Source: 09005aef8086ea0b
dd4c16_32x64h.fm - Rev. E 10/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
cycle; Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current:
BL = 4;
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ, DM, and DQS
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank;
(MAX);
Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
Iout = 0mA
Operating burst write current: BL = 2; Continuous burst writes; One device bank
active; Address and control inputs changing once per clock cycle;
DQ, DM, and DQS inputs changing twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving (BL = 4)
with auto precharge;
change only during active READ or WRITE commands
RC =
t
RC (MIN);
t
t
t
CK =
CK =
t
RC =
CK =
t
t
t
RC (MIN);
CK (MIN); CKE = (LOW)
CK (MIN); CKE = LOW
t
Idd Specifications and Conditions – 128MB (Die Revision K)
Values are for the MT46V16M16 DDR SDRAM only and are computed from values specified in the
256Mb (16 Meg x 16) component data sheet
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle;
t
CK =
t
t
RC =
CK (MIN); DQ, DM, and DQS inputs changing once per clock
t
CK =
t
RC (MIN);
t
CK (MIN); Iout= 0mA; Address and control inputs
t
CK =
t
CK (MIN); Address and control inputs
128MB, 256MB (x64, SR) 200-Pin DDR SDRAM SODIMM
t
CK =
t
t
RFC =
RFC = 7.8125µs
9
t
CK (MIN);
t
t
t
CK =
CK =
RFC (MIN)
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RC =
t
t
CK (MIN);
CK (MIN);
t
RAS
Symbol
Idd4W
Idd3N
Idd5A
Idd2P
Idd3P
Idd4R
Idd2F
Idd0
Idd1
Idd5
Idd6
Idd7
©2003 Micron Technology, Inc. All rights reserved.
1160
-40B
400
480
200
140
240
720
720
640
Idd Specifications
16
24
16
1080
-335
360
460
200
120
220
640
640
640
16
24
16
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA