PDSP2114 OSRAM Opto Semiconductors Inc, PDSP2114 Datasheet - Page 9

• Manufacturer Part Number: PDSP2114
• Description: DISPLAY PROG 8CHAR .200" 5X7 HEG
• Manufacturer: OSRAM Opto Semiconductors Inc
• Series: Alphanumeric Programmable Display™r

Specifications of PDSP2114

• Millicandela Rating: 510µcd
• Size / Dimension: 1.70" L x 0.77" W x 0.21" H (42.67mm x 19.58mm x 5.31mm)
• Color: Green
• Configuration: 5 x 7
• Number Of Digits: 8
• Character Size: 0.2 in
• Illumination Color: High Efficiency Green
• Wavelength: 568 nm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Luminous Intensity: 510 ucd
• Viewing Area (w X H): 2.85 mm x 4.81 mm
• Display Type: 5 x 7 Dot Matrix
• Emitting Color: Hi-Eff. Green
• Digit Size (in): .2in
• Viewing Area Height (mm): 4.81mm
• Package Type: Panel
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Operating Temp Range: -40C to 85C
• Mounting: Through Hole
• Pin Count: 28
• Total Thickness (mm): 5.1mm
• Opto Display Type: Panel
• Pattern Type: Dot Matrix
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Forward (vf) Typ: -
• Internal Connection: -
• Lead Free Status / Rohs Status: Compliant
• Other names: Q68000A8533

Block Diagram
Functional Description
The PDSP211X block diagram is comprised of the following major
blocks and registers.
Display Memory consists of a 8 x 8 bit RAM block. Each of the
eight 8-bit words holds the 7-bit ASCII data (bit D0-D6). The 8th
bit, D7 selects 1 of the 2 pages of character ROM. D7=0 selects
Page 1 of the ROM and D7=1 selects Page 2 of the ROM. A3=1.
RST can be used to initialize display operation upon power up or
during normal operation. When activated, RST will clear the Flash
RAM and Control Word Register (00H) and reset the internal
counter. All eight display memory locations will be set to 20H to
show blanks in all digits.
FL pin enables access to the Flash RAM. The Flash RAM will set
(D0=0) or reset (D0=0) flashing of the character addressed by
A0-A2.
The 1 x 8 bit Control Word RAM is loaded with attribute data
if A3=0.
The Control Word Logic decodes attribute data for proper imple-
mentation.
Character ROM is designed for two pages of 128 characters each.
Both pages of the ROM are Mask Programmable for custom fonts.
On the standard product page one contains standard ASCII,
selected European characters and some scientific symbols. Page
two contains Katakana characters, more European characters, avi-
onics, and other graphic symbols.
The Clock Source could either be the internal oscillator
(CLKSEL=1) of the device or an external clock (CLKSEL=0) could
2006-01-23
RST
CLK I/O
CLKSEL
D7
D6
D5
D4
D3
D2
D1
D0
Address
Lines
A0 A1 A2 A3 WR CE FL
8 x 8 bits
Memory
Display
OSC
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Address Decoder
Flash RAM
Counter
8 x 1 bit
32
Decode
Control
Word
Logic
7-bit
ASCII
Code
Counter
7
MUX Rate
Counter
(4.48 kbits)
128 x 7 bit
Character
Decode
ROM 1
ASCII
128
9
Row Decoder
be an input from another PDSP211X display for the synchroniza-
tion of blinking for multiple displays.
The Display Multiplexer controls the Row Drivers so no additional
logic is required for a display system.
The Display has eight digits. Each digit has 35 LEDs clustered
into a 5 x 7 dot matrix.
Theory of Operation
The PDSP211X Programmable display is designed to work with all
major microprocessors. Data entry is via an eight bit parallel bus.
Three bits of address route the data to the proper digit location in
the RAM. Standard control signals like WR and CE allow the data
to be written into the display.
D0- D7 data bits are used for both ASCII and control word data
input. A3 acts as the mode selector. If A3=0, D0-D7 load the RAM
with control word data. If A3=1, D0-D7 will load the RAM with
ASCII and page select data. In the later mode, D7=0 selects Page
1 of Character ROM and D7=1 selects Page 2 of Character ROM.
For normal operation FL pin should be held high. When FL is held
low, Flash RAM is accessed to set character blinking.
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent out
each display cycle and it takes fourteen display cycles to write into
eight digits.
The rows are being multiplexed in two sets of seven rows each.
The internal timing and control logic synchronizes the turning on of
rows and presentation of column data to assure proper display
operation.
Row Control Logic
& Row Drivers
Blink
Rate
Rows
0 to 13
(4.48 kbits)
128 x 7 bit
Character
Decode
ROM 2
ASCII
Timing &
Control
Logic
0
Column
Data
1
2
Latches
Master
Display
Slave
0 to 8
Digit
3
4
Columns 0 to 19
5
for Digit
Column
Drivers
0 to 8
6
IDBD5068
7