AFBR-5103AZ Avago Technologies US Inc., AFBR-5103AZ Datasheet - Page 19
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AFBR-5103AZ
Manufacturer Part Number
AFBR-5103AZ
Description
TXRX 127MBD DUPLEX SC 1X9
Manufacturer
Avago Technologies US Inc.
Datasheet
1.AFBR-5103TZ.pdf
(20 pages)
Specifications of AFBR-5103AZ
Data Rate
100Mbps
Wavelength
1308nm
Applications
Ethernet
Voltage - Supply
4.75 V ~ 5.25 V
Connector Type
SC
Mounting Type
Through Hole
Function
Implement FDDI and ATM at the 100 Mbps/125 MBd rate
Product
Transceiver
Maximum Rise Time
3 ns, 2.2 ns
Maximum Fall Time
3 ns, 2.2 ns
Pulse Width Distortion
0.02 ns
Maximum Output Current
50 mA
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
SIP-9
For Use With
Multimode Glass
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
13. The transmitter provides compliance with the need for Transmit_Dis-
14. This parameter complies with the FDDI PMD requirements for the
15. This parameter complies with the optical pulse envelope from the FDDI
16. Duty Cycle Distortion contributed by the transmitter is measured at
17. Data Dependent Jitter contributed by the transmitter is specified
18. Random Jitter contributed by the transmitter is specified with an
19. This specification is intended to indicate the performance of the
1
• At the Beginning of Life (BOL)
• Over the specified operating temperature and voltage ranges
• Receiver data window time-width is 2.13 ns or greater and centered
• Input symbol pattern is the FDDI test pattern defined in FDDI PMD
peak power is then calculated by adding 3 dB to the measured
average optical power. The data “0” output optical power is found
by measuring the optical power when the transmitter is driven by a
logic “0” input. The extinction ratio is the ratio of the optical power at
the “0” level compared to the optical power at the “1” level expressed
as a percentage or in decibels.
able commands from the FDDI SMT layer by providing an Output
Optical Power level of < -45 dBm average in response to a logic “0”
input. This specification applies to either 62.5/125 µm or 50/125 µm
fiber cables.
tradeoffs between center wave-length, spectral width, and rise/fall
times shown in Figure 9.
PMD shown in Figure 10. The optical rise and fall times are measured
from 10% to 90% when the transmitter is driven by the FDDI HALT
Line State (12.5 MHz square-wave) input signal.
a 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz square-
wave), input signal. See Application Information - Transceiver Jitter
Performance Section of this data sheet for further details.
with the FDDI test pattern described in FDDI PMD Annex A.5. See
Application Information - Transceiver Jitter Performance Section of
this data sheet for further details.
IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See
Application Information - Transceiver Jitter Performance Section of
this data sheet for further details.
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the following definitions. The Input
Optical Power dynamic range from the minimum level (with a win-
dow time-width) to the maximum level is the range over which the
receiver is guaranteed to provide output data with a Bit Error Ratio
(BER) better than or equal to 2.5 x 10
Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle
base-line wander effect of 50 kHz. This sequence causes a near worst
case condition for inter-symbol interference.
at mid-symbol. This worst case window time-width is the minimum
allowed eye-opening presented to the FDDI PHY PM._Data indication
input (PHY input) per the example in FDDI PMD Annex E. This minimum
window time-width of 2.13 ns is based upon the worst case FDDI PMD
Active Input Interface optical conditions for peak-to-peak DCD (1.0
-10
.
20. All conditions of Note 19 apply except that the measurement is made
21. This value is measured during the transition from low to high levels
22. The Signal Detect output shall be asserted within 100 µs (130 µs for
23. This value is measured during the transition from high to low levels
24. Signal detect output shall be de-asserted within 350 µs after a step
• Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5
ns), DDJ (1.2 ns) and RJ (0.76 ns) presented to the receiver.
condition requires exacting control over DCD, DDJ and RJ jitter compo-
nents that is difficult to implement with production test equipment.
The receiver can be equivalently tested to the worst case FDDI PMD
input jitter conditions and meet the minimum output data window
time-width of 2.13 ns. This is accomplished by using a nearly ideal
input optical signal (no DCD, insignificant DDJ and RJ) and measuring
for a wider window time-width of 4.6 ns. This is possible due to the
cumulative effect of jitter components through their superposition
(DCD and DDJ are directly additive and RJ components are rms ad-
ditive). Specifically, when a nearly ideal input optical test signal is
used and the maximum receiver peak-to-peak jitter contributions
of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns) exist, the minimum
window time-width becomes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns = 4.46
ns, or conservatively 4.6 ns. This wider window time-width of 4.6 ns
guarantees the FDDI PMD Annex E minimum window time-width
of 2.13 ns under worst case input jitter conditions to the Avago
Technologies receiver.
MHz square-wave), input signal to simulate any cross-talk present
between the transmitter and receiver sections of the transceiver.
at the center of the symbol with no window time-width.
of input optical power.
—40°C to 0°C) after a step increase of the Input Optical Power. The
step will be from a low Input Optical Power, —45 dBm, into the range
between greater than P
put will be 10
Detect has been asserted. See Figure 12 for more information.
of input optical power. The maximum value will occur when the input
optical power is either -45 dBm average or when the input optical
power yields a BER of 10
decrease in the Input Optical Power from a level which is the lower
of; -31 dBm or P
was deasserted), to a power level of -45 dBm or less. This step decrease
will have occurred in less than 8 ns. The receiver output will have a
BER of 10
deasserted. The input data stream is the Quiet Line State. Also, signal
detect will be deasserted within a maximum of 350 µs after the BER
of the receiver output degrades above 10
stream that decays with a negative ramp function instead of a step
function. See Figure 12 for more information.
To test a receiver with the worst case FDDI PMD Active Input jitter
-2
or better for a period of 12 µs or until signal detect is
-2
or better during the time, LS_Max (15 µs) after Signal
D
+ 4 dB (P
A
, and —14 dBm. The BER of the receiver out-
-2
D
or better, whichever power is higher.
is the power level at which signal detect
-2
for an input optical data