LTM4601AEV-1#PBF Linear Technology, LTM4601AEV-1#PBF Datasheet - Page 19

• Manufacturer Part Number: LTM4601AEV-1#PBF
• Description: IC DC/DC UMODULE 12A 133-LGA
• Manufacturer: Linear Technology
• Series: µModuler
• Type: Point of Load (POL) Non-Isolatedr

Specifications of LTM4601AEV-1#PBF

• Design Resources: LTM4601A-1 Spice Model
• Output: 0.6 ~ 5 V
• Number Of Outputs: 1
• Power (watts): 60W
• Mounting Type: Surface Mount
• Voltage - Input: 4.5 ~ 20V
• Package / Case: 133-LGA
• 1st Output: 0.6 ~ 5 VDC @ 12A
• Size / Dimension: 0.59" L x 0.59" W x 0.11" H (15mm x 15mm x 2.8mm)
• Power (watts) - Rated: 60W
• Operating Temperature: -40°C ~ 85°C
• Efficiency: 95%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -

APPLICATIONS INFORMATION
Tables 3 and 4 provide a summary of the equivalent θ
for the noted conditions. These equivalent θ
are correlated to the measured values, and are improved
with air fl ow. The case temperature is maintained at 100°C
or below for the derating curves. The maximum case
temperature of 100°C is to allow for a rise of about 13°C
to 25°C inside the μModule with a thermal resistance θ
from junction to case between 6°C/W to 9°C/W. This will
maintain the maximum junction temperature inside the
μModule below 125°C.
Safety Considerations
The LTM4601A modules do not provide isolation from
V
slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
Layout Checklist/Example
The high integration of LTM4601A makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
IN
to V
OUT
. There is no internal fuse. If required, a
PGND
V
V
OUT
IN
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C
OUT
• • •
C
IN
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• • • •
C
JA
• • •
OUT
C
Figure 15. Recommended Layout
IN
parameters
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JA
JC
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• Use large PCB copper areas for high current path, in-
• Place high frequency ceramic input and output capaci-
• Place a dedicated power ground layer underneath the
• To minimize the via conduction loss and reduce module
• Do not put vias directly on pads unless they are capped.
• Use a separated SGND ground copper area for com-
Figure 15 gives a good example of the recommended
layout.
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cluding V
PCB conduction loss and thermal stress.
tors next to the V
high frequency noise.
unit. Refer frequency synchronization source to power
ground.
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
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CONTROL
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LTM4601A/LTM4601A-1
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4601A F15
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IN
, PGND and V
CONTROL
SIGNAL
GND
CONTROL
IN
, PGND and V
OUT
. It helps to minimize the
OUT
pins to minimize
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