DM-COP8/44P National Semiconductor, DM-COP8/44P Datasheet
DM-COP8/44P
Specifications of DM-COP8/44P
Related parts for DM-COP8/44P
DM-COP8/44P Summary of contents
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COP8™ MICROCONTROLLER COP8SAx Designer’s Guide Literature Number 620894-001 January 1997 ...
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REVISION RECORD RELEASE REVISION DATE -001 1/97 ii SUMMARY OF CHANGES First Release ...
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... The information contained in this manual is for reference only and is subject to change without notice. No part of this document may be reproduced in any form or by any means without the prior written consent of National Semiconductor Corporation. COP8, MICROWIRE/PLUS and WATCHDOG are trademarks of National Semiconductor Corporation. PREFACE iii ...
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iv ...
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Chapter 1 MICROCONTROLLER BASICS 1.1 WHAT IS A MICROCONTROLLER 1-1 1.1.1 CPU ...
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Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.8.9 Control ...
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JMP — Jump Absolute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82 2.18.20 JMPL — Jump ...
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... Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-141 Chapter 3 DEVELOPMENT SUPPORT 3.1 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 iceMASTER (IM) IN-CIRCUIT EMULATION . . . . . . . . . . . . . . . . . . . . . 3-1 3.3 IceMASTER DEBUG MODULE (DM 3-3 3.4 IceMASTER EVALUATION PROGRAMMING UNIT (EPU 3-5 3.4.1 Getting Started With the EPU . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5 COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL KIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.6 COP8 C COMPILER ...
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BATTERY-POWERED WEIGHT MEASUREMENT . . . . . . . . . . . . . . . 4-22 4.8 ZERO CROSS DETECTION . . . . . . . . . . . . . . . . ...
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Figure 1-1 Microcontroller General Block Diagram 1-2 Figure 1-2 Microcontroller Operation . . . . . ...
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... Figure 3-2 COP8-DM Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Figure 3-3 EPU-COP8 Tool Environment 3-5 Figure 4-1 Test Circuit 4-2 Figure 4-2 Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Figure 4-3 MICROWIRE/PLUS Sample Protocol Timing . . . . . . . . . . . . . . . . . . . . 4-4 Figure 4-4 NM93C06-COP8SAx7 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Figure 4-5 Timer PWM Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Figure 4-6 PWM Motor Control ...
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CONTENTS ...
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WHAT IS A MICROCONTROLLER? Microcontroller is an highly integrated single-chip microcomputer. Some of the key elements of a microcontroller include a CPU to process information, program memory to store instructions, data memory to store information, system timing, and input/output ...
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Program Memory CPU Figure 1-1 Microcontroller General Block Diagram 1.2 WHAT DOES A MICROCONTROLLER REPLACE? A ...
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WHAT ARE MICROCONTROLLER APPLICATIONS? Microcontrollers applications ...
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Market Segment Consumer Children Basketball/Baseball Toys and Games Games Children Electronic Toys Darts Throws Juke Box Pinball Laser Gun Electronic Audio Greeting Cards Audio Items Electronic Musical Equipment Electronic Small Appliances: Appliances Irons and Tools Coffee Makers Digital Scales Microwave ...
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Market Segment Applications Personal Communications Cordless Phone (base/handset) Phone Dialer Answering Machine Feature Phone PBX Card CB Radios/Digital Tuners Cable Converter Medical Monitors Thermometer Pressure Monitors Various Portable Monitors Medical Bed-side Pump/Timers Equipment Ultrasonic Imaging System Analyzers (chemical, data) Electronic ...
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Market Segment Applications Automotive Radio/Tape Deck Controls Window, Seat, Mirror, and Door Controls Climate Controls Headlight/Antenna Power Steering Anti Theft Slave Controllers 1.4 WHAT IS THE DIFFERENCE BETWEEN A MICROCONTROLLER AND A MICROPROCESSOR? The broad category of microcomputers is divide ...
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This means that an instruction fetch cannot overlap a data access from memory. The obvious advantage of a Von Neumann ...
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Program Memory Address Register CPU Data Register Figure 1-2 Microcontroller Operation 1-8 MICROCONTROLLER BASICS Data Bus Data Memory Address Bus I/O ...
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Program Memory Program memory contains the microcontroller program. There are several types of program memory—ROM, OTP/EPROM, EEPROM. Stack Figure 1-3 Program Memory Section Structure The number of bits per address location and number of memory locations varies from one ...
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Each byte in program memory contains an instruction like ADD or JMP, represented by a code or opcode (example: 033 = ADD). Instructions are stored in the order to be executed. For example: LD A,#00 INC A JMP 00 These ...
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Data Memory Memory Address Register Figure 1-4 Separate Data and Code Space data memory. The data pointer (PTR) is loaded with the address of a byte of data in memory. To access the byte of data, the pointer can be ...
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POP instructions. Stack Pointer 1.7.3 Microcontroller CPU The key function of a CPU is to perform instruction fetch/decode/execute. Fetch The program counter (PC) addresses a location in program memory con- taining an instruction. This instruction is latched into a special ...
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Timer run, which tells microcontroller to start the timer. Accumulator vs Register An accumulator-based microcontroller operates in a manner different from a register- based microcontroller. The difference is due to the different ALU architectures. The most common are: 1. ...
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Addent #1 Addent #2 Figure 1-6 Adding Two Numbers Using Register Based Machine However, the accumulator-based machine requires operands to be moved into the accumulator before instructions are executed. Which takes longer in the end? It depends on how much ...
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External Interrupt Internal Interrupts Software Traps Maskable vs. Non-Maskable Interrupts 1.7.4 Timing The microcontroller uses the instruction cycle time as an internal timing reference. The instruction cycle time is the amount of time it takes for an instruction to be ...
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External Clock Circuitry Clock Generator 1.7.5 Oscillator Circuits Typically there are three types of clock oscillator options available: external oscillator, R/C oscillator, or crystal oscillator. External Oscillator An external square wave clock source is generated outside and presented to the ...
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As compared with other oscillator circuits, this circuit is not disturbed very much by connecting a scope probe at any point in the circuit, ...
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Latches Ports Memory Mapped I/O or Ports User-Configurable I/O Dedicated I/O 1-18 MICROCONTROLLER BASICS output voltage on the pin corresponds to a single bit of information. Often used to store outgoing/incoming bits. A port is a group of pins used ...
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Each microcontroller has a set of instructions. The user can organize particular instructions in a logical order to create a program. The microcontroller follows this program to perform a given task. The contents of a microcontroller instruction set vary with ...
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Register Indirect Post-Increment or Post-Decrement Indexed Addressing 1.7.7 Programming Routines/Subroutines A routine is a segment of code which performs a specific function. A subroutine is a segment of code which performs a specific part of function. A subroutine is usually ...
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Interrupt Routines There are two methods to get the interrupt routines: 1. Without a Vector Table Polling—All interrupts cause an immediate jump to a single location in mem- ...
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Saving and restoring of the microcontroller state during interrupts or when switching between different tasks. Example of an interrupt routine: INTERRUPT; PUSH A PUSH CNTRL PUSH PSW IFBIT 0, IPND JP TIMERINT IFBIT 1, IPND JP EXTERNALINT IFBIT 2, IPND ...
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Assembler The assembler is a software program that converts a source program into an object file. In other words, it converts ASCII representation of instructions to binary representation. 2. Assembler Inputs/Outputs Source File - ASCII file containing a software ...
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Linker The linker is a software program that combines separate object files produced by the assembler into a single object file. The linker allows the user to create separate code modules for different sections of code. It also allows ...
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A simulator is software program/model which acts like a hardware device. Code written for the device is executed in the software model exactly as it would be executed in the device. Key features of a simulator include: 1. Can execute ...
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Following is the typical path for developing microcontroller programs: 1-26 MICROCONTROLLER BASICS EDITOR ENTER PROGRAM COMPILE PROGRAM ASSEMBLE PROGRAM LINK PROGRAM SIMULATE PROGRAM EMULATE PROGRAM WITH TARGET SYSTEM ...
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INTRODUCTION The COPSAx7 OTP microcontrollers are members of the COP8™ feature family using an 8-bit single chip core architecture. These devices are fabricated in National Semiconductor’s high-density EPROM process, and offered in a variety of packages, temperature ranges, and ...
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Device EPROM RAM COP8SAC7 4k COP8SAB7 2k COP8SAA7 1k 2.2.1 CPU Features • Versatile, easy-to-use instruction set • instruction cycle time • Eight multi-source vectored interrupts — External Interrupt — Idle Timer T0 — One Timer (with 2 ...
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Multi-Input Wakeup Logic • One 16-bit timer with two 16-bit registers supporting: — Processor Independent PWM mode — External Event counter mode — Input Capture mode • Idle Timer • MICROWIRE/PLUS™ Serial Interface (SPI Compatible) 2.2.3 I/O Features • ...
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C 8 BIT CORE CLOCK MODIFIED HARVARD HALT ARCHITECTURE IDLE WAKEUP 16 BIT RESET TIMER T1 INTERRUPT A INSTR B DECODE LOGIC X SP PSW ILLEGAL ICNTRL COND DETECT CNTRL CPU REGISTERS Figure 2-1 COP8SAx7 Block Diagram 2.4 ARCHITECTURE The ...
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G4/ G5/ G6/ G7/CKO 16-PIN 5 12 CKI DIP/ Top View G4/ G5/ G6/ G7/CKO 4 ...
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CKI 44-PIN F2 11 PLCC ...
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EPROM Temperature Order Number 0˚C to +70˚C COP8SAA716M9 COP8SAA720M9 COP8SAA728M9 COP8SAA716N9 COP8SAA720N9 COP8SAA728N9 –40˚C to +85˚C COP8SAA716M8 COP8SAA720M8 COP8SAA728M8 COP8SAA716N8 COP8SAA720N8 COP8SAA728N8 –40˚C to +125˚C 2k EPROM Order Number Order Number 16M 20M COP8SAB720M9 20M COP8SAC720M9 28M COP8SAB728M9 28M ...
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COPSAx7 I/O structure minimizes external component requirements. Software- switchable I/O enables designers to reconfigure the microcontroller's I/O functions with a single instruction. Each individual I/O pin can be independently configured as an output pin low, an output high, an input ...
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Figure 2-4 I/O Port Configurations Port ...
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G0 INTR (External Interrupt Input) G2 T1B (Timer T1 Capture Input) G3 T1A (Timer T1 I/ (MICROWIRE Serial Data Output (MICROWIRE Serial Clock (MICROWIRE Serial Data Input) Port G has the following dedicated functions: ...
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Figure 2-6 I/O Port Configurations–Input Mode 2.8 FUNCTIONAL DESCRIPTION ...
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Program Counter (PC). 2.8.2 Program Memory The program memory consists of 1024, 2048, or 4096 bytes of EPROM. Table 2-1 shows the program memory sizes for the different devices. These bytes may hold program instructions or constant data (data ...
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The ECON register is used to configure the user selectable clock, security, RAM size, power-on reset, WATCHDOG, and HALT options. The register can be programmed and read only in EPROM programming mode. Therefore, the register should be programmed at the ...
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Place data in the 8-bytes of user storage space Data .USER=0x01 0x02 0x03 m0x04 0x05 0x06 0x07 0x08 2. Place assembly date in 8-bytes of user storage space Date is ...
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The device is initialized when the RESET pin is pulled low or the On-chip Power-On Reset is enabled. EXTERNAL ON-CHIP POWER-ON RESET The following occurs upon initialization: Port L: TRISTATE Port C: TRISTATE Port G: TRISTATE Port F: TRISTATE Port ...
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UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on WATCHDOG (if enabled): The device comes out of reset with both the WATCHDOG logic and ...
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VCC (min). The desired response is shown in Figure 2-9. Volts V (min (R) IL Figure 2-9 Dddesired Reset Response Time On-chip Power-On Reset The on-chip reset circuit is selected by a bit in the ECON ...
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On-Chip Reset V /RESET max t min Figure 2-10 Reset Timing (Power-On Reset enabled) With V Figure 2-11 Reset Circuit Using Power-On Reset 2-18 COP8SAx7 MICROCONTROLLER NOT ACTIVE ACTIVE x is the minimum operating voltage for the ...
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There are four clock oscillator options available: Crystal Oscillator with or without on chip bias resistor, R/C Oscillator with on-chip resistor and capacitor, and External Oscillator. The oscillator feature is selected by programming the ECON register, which is summarized in ...
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The External Oscillator mode can be selected by programming ECON Bit and ECON Bit CKI can be driven by an external clock signal provided it meets the specified duty cycle, rise and fall times, ...
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C For operation at lower than maximum R/C oscillator frequence 2.8.9 Control Registers CNTRL Register (Address X'00EE) The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: SL1 & SL0 Select the MICROWIRE/PLUS clock divide by ( ...
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The PSW register contains the following select bits: GIE Global interrupt enable (enables interrupts) EXEN Enable external interrupt BUSY MICROWIRE/PLUS busy shifting flag EXPND External interrupt pending T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge ...
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The device contains a very versatile set of timers (T0, T1). Timer T1and associated autoreload/capture registers power up containing random data. 2.9.1 Timer T0 (IDLE Timer) The device supports applications that require maintaining real time and low power with the ...
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The timer can generate the PWM output with the width and duty cycle controlled by the values stored in the reload registers. The reload registers control the countdown values and the reload values are automatically written ...
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PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output. Mode 2. External Event Counter Mode This mode ...
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The capture register eliminates the latency time, thereby allowing the applications program to retrieve the timer value stored in the capture register. In this mode, the timer T1 is constantly ...
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The control bits and their functions are summarized below. T1C0 Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter), where 1 = Start Stop Timer Underflow Interrupt Pending Flag in Mode 3 ...
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Today, the proliferation of battery-operated based applications has placed new demands on designers to drive power consumption down. Battery- operated systems are not the only type of applications demanding low power. The power budget constraints are also imposed on those ...
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Wakeup signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with the tc instruction cycle clock. The tc clock is derived by dividing the oscillator clock down by a ...
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Multi-Input Wakeup from the L Port. Alternately, the microcontroller resumes normal operation from the IDLE mode when the twelfth bit (representing 4.096 ms at internal clock frequency of 10 MHz, t This toggle condition of the twelfth bit ...
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The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate edge selectable external interrupts. Figure 2-20 shows the Multi-Input ...
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CONTINUOUS SCANNING START SCAN KEYBOARD CHANGE? KEY DECODING KEY ENCODING OUTPUT MIMW typically reduces current consumption down to less than 4 A during quiescent states — compared current consumption if code remained running. In addition, MIWU ...
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This selection is made via the register WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting ...
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Hex. The Software trap has the highest priority while the default VIS has the lowest priority. Each of the six maskable inputs has a fixed arbitration ...
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The enable bit associated with that interrupt is set. 2. The GIE bit is set. 3. The device is not processing a non-maskable interrupt. (If a non-maskable in- terrupt is being serviced, a maskable interrupt must wait until that ...
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Within a specific interrupt service routine, the associated pending bit should be cleared. This is typically done as early as possible in the service routine in order to avoid missing the next occurrence of the same type ...
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ARBITRATION SOURCE RANKING (1) Highest Software (2) Reserved (3) External (4) Timer T0 (5) Timer T1 (6) Timer T1 (7) MICROWIRE/PLUS (8) Reserved (9) Reserved (10) Reserved (11) Reserved (12) Reserved (13) Reserved (14) Reserved (15) Port L/Wakeup (16) Lowest ...
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Although it is possible to poll the pending bits to detect the source of an interrupt, this practice is not recommended. The use of polling allows the standard arbitration ranking to be altered, but the ...
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VIS STPND SET? EXTERNAL INTERRUPT ACTIVE? PORT L/ WAKEUP INTERRUPT ACTIVE? JUMP TO VECTOR AT 0yE0/0yE1 END The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) and upon RESET. JUMP TO ...
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Programming Example: External Interrupt PSW CNTRL RBIT RBIT SBIT SBIT SBIT WAIT .=0FF VIS . . . .=01FA .ADDRW SERVICE . . . SERVICE: RBIT, EXPND, PSW . . . RET I 2-40 COP8SAx7 MICROCONTROLLER =00EF ...
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Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending flag is reset to zero when a device Reset ...
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Software Trap routine is interrupted by another Software Trap, the RPND instruction in the service routine for the second Software Trap will reset the STPND flag; upon return to the first Software Trap routine, the STPND flag will have the ...
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A maskable interrupt routine should end with an RETI instruc- tion. 2.14 WATCHDOG/CLOCK MONITOR The devices contain a user selectable WATCHDOG and clock monitor. The following section ...
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WDSVR Bit 2.14.1 Clock Monitor The Clock Monitor aboard the device can be selected or deselected under program control. The Clock Monitor is guaranteed not to reject the clock if the instruction cycle clock (1/t ...
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Key Data Window Data Match Match Don't Care Mismatch Mismatch Don't Care Don't Care Don't Care state. Upon triggering the WATCHDOG, the logic will pull the WDOUT (G1) pin low for an additional 16 tc–32 tc cycles after the signal ...
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WDSVR. Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0's. • The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes. • The CLOCK MONITOR ...
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Hex. This is an undefined ROM location and the instruction fetched (all 0's) from this location will generate a software interrupt signaling an ...
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MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In the master mode, the SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. Table 2-9 details the different ...
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This table assumes that the control flag MSEL is set. G4 (SO) G5 (SK) Config. Bit Config. Bit MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an ...
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Port (SKSEL) Phase Config. Bit Normal 0 Alternate 1 Alternate 0 Normal 1 SK Bit 7 Out Bit 6 SO (MSB) Bit Bit 6 (MSB) Figure 2-26 MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK ...
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SK Bit 7 Out Bit 6 SO (MSB) Bit Bit 6 (MSB) Figure 2-28 MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode Bit 7 SO (MSB) Bit 7 SI (MSB) Figure 2-29 MICROWIRE/PLUS SPI Mode ...
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All RAM, ports and registers (except A and PC) are mapped into data memory address space. RAM Select 64 On-chip RAM Bytes. Selected by ECON Register 128 On-chip RAM Bytes. 2-52 COP8SAx7 MICROCONTROLLER Address ADD REG On-chip ...
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Address RAM Select Reading any undefined memory location in the address range of 0080H–00FFH will return undefined data. ADD REG DB Reserved DC Port D Reserved Reserved E6 Timer T1 Autoload ...
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Introduction This section defines the instruction set of the COPSAx7 Family members. It contains information about the instruction set features, addressing modes and types. 2.17.2 Instruction Features The strength of the instruction set is based on the following features: ...
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Each addressing mode has its own advantages and disadvantages with respect to flexibility, execution speed, and program compactness. Not all modes are available with all instructions. The Load (LD) instruction offers the largest number of addressing modes. The available ...
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B Register or X register (pointer register). The pointer register is automatically incremented or decremented after execution, allowing easy manipulation of memory blocks with software loops. In assembly language, the notation ...
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Example: Load Accumulator Indirect LAID Reg/Data Memory PCU PCL Accumulator Memory Location 041F Hex Transfer-of-Control Addressing Modes Program instructions are usually executed in sequential order. However, Jump instructions can be used to change the normal execution sequence. ...
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The distance of the jump can range from –31 to +32. A JP+1 instruction is not allowed. The programmer should use a NOP instead. Example: Jump Relative JP 0A Reg ...
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Accumulator serving as the low order byte of a pointer into program memory. For purposes of accessing program memory, the contents of the Accumulator are written to PCL (temporarily). The ...
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The instruction set contains a wide variety of instructions. The available instructions are listed below, organized into related groups. Some instructions test a condition and skip the next instruction if the condition is not true. Skipped instructions are executed as ...
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Vector Interrupt Select (VIS) Load and Exchange Instructions The load and exchange instructions write byte values in registers or memory. The addressing mode determines the source of the data. Load (LD) Load Accumulator Indirect (LAID) Exchange (X) Logical Instructions The ...
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The conditional instructions test a condition. If the condition is true, the next instruction is executed in the normal manner; if the condition is false, the next instruction is skipped. If Equal (IFEQ) If Not Equal (IFNE) If Greater Than ...
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COP8 cross-assembler: A Accumulator Pointer, located in RAM register memory location 00FE. [B] Contents of RAM data memory location indicated by B pointer. [B+] Same as [B], except that B pointer is post-incremented. [B-] Same ...
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Syntax: a)ADC A,[B] b)ADC A,# c)ADC A,MD Description: The contents of a) the data memory location referenced by the B pointer b) the immediate value found in the second byte of the instruction c) the data memory location referenced by ...
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Syntax: a)ADD A,[B] b)ADD A,MD c)ADD A,# Description: The contents of the data memory location referenced by a) the B pointer b) the address in the second byte of the instruction c) the immediate value found in the second byte ...
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Syntax: a)AND A,[B] b)AND A,# c)AND A,MD Description: An AND operation is performed on corresponding bits of the accumula- tor and a) the contents of the data memory location referenced by the B pointer. b) the immediate value found in ...
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Syntax: ANDSZ A,# Description: An AND operation is performed on corresponding bits of the accumula- tor and the immediate value found in the second byte of the instruction. If the result is zero, the next instruction is skipped. The accumulator ...
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Syntax: CLR A Description: The accumulator is cleared to all zeros. Operation: A <- 0 Instruction Addressing Mode CLR A Implicit 2-68 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycle ...
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Syntax: DCOR A Description: This instruction when used following an ADC (add with carry) or SUBC (subtract with carry) instruction will decimal correct the result from the binary addition or subtraction. Note that the ADC instruction must be preceded with ...
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Syntax: DECA Description: This instruction decrements the contents of the accumulator and places the result back in the accumulator. The Carry and Half Carry flags re- main unchanged. Operation: A < Instruction Addressing Mode DEC A Implicit ...
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Syntax: DRSZ REG# Description: This instruction decrements the contents of the selected memory regis- ter (selected by #, where # = and places the result back in the same register. If the result is zero, the next ...
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Syntax: a)IFBIT #,[B] b)IFBIT #,MD c)IFBIT #,A Description: The selected bit (# = with 7 being the high-order bit) from a) the memory location reference by the B pointer is tested. b) the memory location referenced by ...
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Syntax: IFBNE # Description: If the low-order nibble of the B pointer is not equal to # (where # = 0 to F), then the next instruction is executed. Otherwise, the next instruction is skipped. This instruction is useful where ...
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Syntax: IFC Description: The next Instruction is executed if the Carry flag is found set. Otherwise, the next instruction is skipped. The Carry flag is left unchanged. Operation CARRY (C = 0), THEN SKIP NEXT INSTRUCTION Instruction Addressing ...
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Syntax: a)IFEQ A,[B] b)IFEQ A,# c)IFEQ A,MD d)IFEQ MD,# a) The contents of the data memory location referenced by the B pointer are compared for equality with the contents of the accu- mulator. b) The immediate value found in the ...
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Syntax: a)IFGT A,[B] b)IFGT A,# c)IFGT A,MD Description: The contents of the accumulator are tested for being greater than a) the contents of the data memory location referenced by the B pointer. b) the immediate value found in the second ...
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Syntax: IFNC Description: The next instruction is executed if the Carry flag is found reset. Other- wise, the next instruction is skipped. The Carry flag is left unchanged. Operation: IF CARRY (C=1), THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode IFNC ...
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Syntax: a)IFNE A,[B] b)IFNE A,# c)IFNE A,MD Description: a) The contents of the data memory location referenced by the B pointer are compared for inequality with the contents of the ac- cumulator. b) The immediate value found in the second ...
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Syntax: INC A Description: This instruction increments the contents of the accumulator and places the result back in the accumulator. The Carry and Half Carry flags re- main unchanged. Operation: A < Instruction Addressing Mode INC A ...
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Syntax: INTR Description: This zero opcode software trap instruction first stores its return address in the data memory software stack and then branches to program mem- ory location 00FF. This memory location is the common switching point for all COP888 ...
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Syntax: JID Description: The JID instruction uses the contents of the accumulator to point to an indirect vector table of program addresses. The contents of the accumu- lator are transferred to PCL (Lower 8 bits of PC), after which the ...
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Syntax: JMP ADDR Description: This instruction jumps to the programmed memory address. The value found in the lower nibble (4 bits) of the first byte of the instruction is transferred to the lower nibble of PCU (Upper 7 bits of ...
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Syntax: JMPL ADDR Description: The JMPL instruction allows branching to anywhere in the 32-Kbyte program memory space. The values found in the second and third bytes of the instruction are transferred to PCU (Upper 7 bits of PC) and PCL ...
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Syntax: JP DISP Description: The relative displacement value found in the instruction opcode (all 8 bits) is added to the Program Counter (PC). The normal PC incrementa- tion is also performed. The displacement value allows a branch back from 0 ...
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Syntax: JSR ADDR Description: This instruction pushes the return address onto the software stack in data memory and then jumps to the subroutine address. The contents of PCL (Lower 8 bits of PC) are transferred to the data memory location ...
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Syntax: JSRL ADDR Description: The JSRL instruction allows the subroutine to be located anywhere in the 32-Kbyte program memory space. The instruction pushes the return address onto the software stack in data memory and then jumps to the subroutine address. ...
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Address Mode: INDIRECT Description: The LAID instruction uses the contents of the accumulator to point to a fixed data table stored in program memory. The data table usually rep- resents a translation matrix, such as the input from a keyboard ...
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Syntax: a)LD A,[B] b)LD A,[B+] c)LD A,[B-] d)LD A,# e)LD A,MD f)LD A,[X] g)LD A,[X+] h)LD A,[X-] Description: a) The contents of the data memory location referenced by the B pointer are loaded into the accumulator. b) The contents of ...
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Instruction Addressing Mode LD A,[B] Register Indirect (B Pointer) LD A,[B+] Register Indirect With Post- Incrementing B Pointer LD A,[B-] Register Indirect With Post- Decrementing B Pointer LD A,# Immediate LD A,MD Memory Direct LD A,[X] Register Indirect (X Pointer) ...
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Syntax B,# (# < 16 B,# (# > 15) Description: a) The one’s complement of the value found in the lower nibble (4 bits) of the instruction is transferred to the lower-nibble position of the B ...
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Syntax: a)LD [B],# b)LD [B+],# c)LD [B-],# d)LD MD,# Description: a) The immediate value found in the second byte of the instruction is loaded into the data memory location referenced by the B pointer. b) The immediate value found in ...
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Syntax: LD REG,# Description: The immediate value found in the second byte of the instruction is load- ed into the data memory register referenced by the low-order nibble of the first byte of the instruction. Operation: REG <- # Instruction ...
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Syntax: NOP Description: No operation is performed by this instruction, so the net result is a delay of one instruction cycle time. Operation: NO OPERATION Instruction Addressing Mode NOP Implicit Instruction Bytes Hex Op Code Cycles 1 1 COP8SAx7 MICROCONTROLLER ...
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Syntax: a)OR A,[B] b)OR A,# c)OR A,MD Description operation is performed on corresponding bits of the accumulator with a) the contents of the data memory location referenced by the B pointer. b) the immediate value found in the ...
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Syntax: POP A Description: The Stack Pointer (SP) is incremented, and then the contents of the data memory location referenced by the SP are transferred to the accumula- tor. Operation: SP < <- [SP] Instruction Addressing ...
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Syntax: PUSH A Description: The contents of the accumulator are transferred to the data memory lo- cation referenced by the Stack Pointer (SP), and then the SP is decre- mented. Operation: [SP] < < Instruction ...
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Syntax: a)RBIT #,[B] b)RBIT #,MD Description: The selected bit (# = with 7 being the high-order bit) of the data memory location referenced by the a) B pointer is reset address in the second ...
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Syntax: RC Description: Both the Carry and Half Carry flags are reset to 0. Operation: C < <- 0 Instruction Addressing Mode RC Implicit 2-98 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
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Syntax: RET Description: The Stack Pointer (SP) is first incremented. The contents of the data memory location referenced by SP are then transferred to PCU (Upper 7 bits of PC), after which SP is again incremented. Next, the contents of ...
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Syntax: RETI Description: The Stack Pointer (SP) is first incremented. The contents of the data memory location referenced by SP are then transferred to PCU (Upper 7 bits of PC), and SP is again incremented. Next, the contents of the ...
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Syntax: RETSK Description: The Stack Pointer (SP) is first incremented. The contents of the data memory location referenced by SP are then transferred to PCU (Upper 7 bits of PC), and SP is again incremented. Next, the contents of the ...
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Address Mode: RLC A Description: The contents of the accumulator and Carry flag are rotated left one bit position, with the Carry flag serving as a ninth bit position linking the ends of the 8-bit accumulator. The previous carry is ...
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Syntax: RPND Description: The RPND instruction resets the Non-Maskable Interrupt Pending flag (NMIPND) provided that the NMI interrupt has already been acknowl- edged and the Software Trap Pending flag was not found set. Also, RPND unconditionally resets the Software Trap ...
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Address Mode: RRC A Description: The contents of the accumulator and Carry flag are rotated right one bit position, with the Carry flag serving as a ninth bit position linking the ends of the 8-bit accumulator. The previous carry is ...
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Syntax: a)SBIT #,[B] b)SBIT #,MD Description: The selected bit (# = with 7 being the high-order bit) of the data memory location referenced by the a) B pointer is set address in the second ...
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Syntax: SC Description: Both the Carry and Half Carry flags are set to 1. Operation: C < <- 1 Instruction Addressing Mode SC Implicit 2-106 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
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Syntax: a)SUBC A,[B] b)SUBC A,# c)SUBC A,MD Description: a) The contents of the data memory location referenced by the B pointer are subtracted from the contents of the accumulator, and the result is simultaneously decremented if the Carry flag is ...
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Syntax: SWAP A Description: The upper and lower nibbles of the accumulator are exchanged. Operation: A(7-4) <--> A Instruction Addressing Mode SWAP A Implicit 2-108 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
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Syntax: VIS Description: The purpose of the VIS instruction is to vector to the interrupt service routine for the interrupt with the highest priority and arbitration rank- ing that is currently enabled and requesting. The VIS instruction expe- dites this ...
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Syntax: a)X A,[B] b)X A,[B+] c)X A,[B-] d)X A,MD e)X A,[X] f)X A,[X+] g)X A,[X-] Description: a) The contents of the data memory location referenced by the B pointer are exchanged with the contents of the accumulator. b) The contents ...
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B; B < c)A <-> < d)A <-> MD e)A <-> X f)A <-> < g)A <-> < Instruction Addressing ...
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Syntax: a)XOR A,[B] b)XOR A,# c)XOR A,MD Description: An XOR (Exclusive OR) operation is performed on corresponding bits of the accumulator with a) the contents of the data memory location referenced by the B pointer. b) the immediate value found ...
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The following abbreviations represent the nomenclature used in the instruction description and the COP8 cross-assembler A 8-Bit Accumulator Register B 8-Bit Address Register X 8-Bit Address Register SP 8-Bit Stack Pointer Register PC 15-Bit Program Counter Register PU Upper 7 ...
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ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical EXclusive OR IFEQ MD,Imm IF EQual IFEQ A,Meml ...
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Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes ...
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Instructions Using A & C CLRA INCA DECA LAID DCORA RRCA RLCA SWAPA SC RC IFC IFNC PUSHA POPA ANDSZ Memory Transfer Instructions Register Indirect [B] X A,* 1/1 LD A,* 1/1 LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD ...
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LOWER NIBBLE COP8SAx7 MICROCONTROLLER 2-117 ...
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This section is intended overview of programming examples. For more detailed and varied programming examples, refer to the Microontroller COP8 Databook. 2.19.1 Clear RAM The following program clears all RAM locations in the base segment except for ...
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BINARY ADDITION LD X,#16 LD B,#24 RC LOOP: LD A,[X+] ADC A,[B] X A,[B+] IFBNE #12 JP LOOP IFC JP OVFLOW BINARY SUBTRACTION LD X,#010 LD B,#018 SC LOOP: LD A,[X+] SUBC A,[B] X A,[B+] IFBNE ...
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The following program examples illustrate “adding machine” type operations where the result replaces the first operand. With subtraction, this entails the result replacing the minuend rather ...
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SUM, and then subtracts the SUM from a two-byte total TOT. Assume that the table is located starting a program memory address 0401, while SUM and TOT are at RAM data memory locations 1, 0 ...
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MULTIPLY (16X16) SUBROUTINE MULTIPLICAND IN [1,0] MULTIPLIER IN [3,2] PRODUCT IN [ .SECT MEMCNT, REG CNTR: .DSB 1 .SECT CODE, ROM MULT: LD CNTR,#17 LD B,#4 LD [B+],#0 LD [B],#0 LD X,#0 RC MLOOP: LD A,[B] RRC ...
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DIVIDE (16 16) SUBROUTINE DIVIDEND IN [3,2] DIVISOR IN [1,0] QUOTIENT IN [3,2] REMAINDER IN [5,4] .SECT MEMCNT, REG CNTR: .DSB 1 .SECT CODE, ROM DIV: LD CNTR,#16 LD B,#5 LD [B-],#0 LD [B],#0 LD X,#4 LSHFT B,#2 ...
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JP jump to LUP instruction in order to minimize program size. DIVIDE (24 8) SUBROUTINE DIVIDEND IN [2,1,0] DIVISOR IN [4] QUOTIENT IN [2,1,0] REMAINDER IN [3] .SECT MEMCNT, REG CNTR: .DSB 1 .SECT CODE, ROM DIV: ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin ESD Protection Level Total Current into V Pin (Source) CC Total ...
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Parameter Source (Push-Pull Mode) Sink (L0-L3, Push-Pull Mode) Sink (L4-L7, Push-Pull Mode) All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) Allowable Sink Current per Pin (Note 6) D Outputs and All others Maximum ...
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Parameter Instruction Cycle Time ( Crystal/Resonator, External Internal R/C Oscillator R/C Oscillator Frequency Variation (Note 6) External CKI Clock Duty Cycle (Note 6) Rise Time (Note 6) Fall Time (Note 6) Inputs t SETUP t HOLD Output ...
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If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin ESD Protection Level Total Current into V Pin (Source) CC Total Current out of ...
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Parameter All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) Allowable Sink Current per Pin (Note 6) D Outputs and All others Maximum Input Current without Latchup (Note 4) RAM Retention Voltage, Vr rise ...
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AC Electrical Characteristics specified) Parameter Instruction Cycle Time ( Crystal/Resonator, External Internal R/C Oscillator R/C Oscillator Frequency Variation (Note 6) External CKI Clock Duty Cycle (Note 6) Rise Time (Note 6) Fall Time (Note 6) Inputs t ...
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If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin ESD Protection Level Total Current into V Pin (Source) CC Total Current out of ...
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Parameter Allowable Sink Current per Pin (Note 6) D Outputs and All others Maximum Input Current without Latchup (Note 4) RAM Retention Voltage, Vr rise time from a 2. Input Capacitance Load Capacitance ...
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Parameter Instruction Cycle Time ( Crystal/Resonator, External Internal R/C Oscillator R/C Oscillator Frequency Variation (Note 6) External CKI Clock Duty Cycle (Note 6) Rise Time (Note 6) Fall Time (Note 6) Inputs t SETUP t HOLD Output ...
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National’s patent ESD protection and EMI reduction circuits are implemented on device to address ESD/EMI problems. 2.22 INPUT PROTECTION The COP8SAx7 input pins have internal circuitry for protection from ESD. The internal circuitry is shown in Figure 2-31. Figure 2-31 ...
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ESD pulse on an input pin, onto the V bus. Figure 2-33 shows the on-chip detection/protection circuit. The circuitry is designed to meet ESD protection goal of at least 2000 volts as measured using ...
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... Freq is the frequency in MHz • and the perimeter of the loop P << . Applying this equation to a single standard output for a National Semiconductor Microcontroller, and performing a Fourier analysis of the output switching at a frequency of 20 MHz, yields the results shown in Table 2-12. These calculations assume a trace length of 5 inches, a board thickness of 0 ...
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Harmoni c (MHz 100 120 140 160 180 but usually several at one time, thus adding the effective magnetic fields from all the outputs which are switching. Accurate analysis requires characterization of the noise present at ...
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The best way to provide a ground plane is through the use of a multilayer printed circuit board. The large area and the proximity of the V decoupling for the power, and provide effective return paths for both power and ...
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Ferrite beads are very effective for this type of decoupling due to their lossy nature. Rather than storing the energy and returning it to the circuit later, ferrites will ...
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The COP8SAx7 devices electromagnetic interference designs. National’s patented EMI reduction technology offers low EMI emissive clock circuitry, EMI-optimized pinouts, gradual turn-on output drivers (GTOs) and an on-chip choke device to help circumvent many of the EMI issues influencing embedded control ...
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National’s design goal was to reshape the IC pin current waveforms from their original values. A second goal was to provide separate power and ground bus systems on-chip for each of the following groups: Chip digital logic, Chip I/O buffers, ...
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Pin GND GND Pin DGND Figure 2-35 Block diagram of EMI Circuitry 2-142 COP8SAx7 MICROCONTROLLER Choke Clock Device Oscillator Chip Nucleus Level Logic Shifting CKI CKO Gradual Turn On OUTPUT Input INPUT ...
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SUMMARY • iceMASTER: IM-COP8/400 -- Full featured in-circuit emulation for all COP8 prod- ucts. A full set of COP8 Basic and Feature Family device and package specific probes are available. • COP8 Debug Module: Moderate-cost in-circuit emulation and development ...
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Figure 3-1 COP8 iceMASTER Environment • Full 4k frame synchronous trace memory. Address, instruction, and eight unspec- ified, circuit connectable trace lines. Display can be high-level language source (e.g., C source), assembly, or mixed. • A full 64k hardware configurable ...
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... Corporation to support the whole COP8 family of products. National and National authorized Distributors are resale vendors for these products. See Figure 3-2 for the iceMASTER Debug Module configuration. Figure 3-2 COP8-DM Environment Base Unit iceMASTER base unit, 110V Power Supply iceMASTER base unit, 220V Power Supply iceMASTER Probe, COPSAx7 44 PLCC, 2.7 – ...
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COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product families. It offers the following features: • Real-time in-circuit emulation; full operating voltage range operation, full DC- ...
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... COP8SA-DM Cable Adapters, requires one for emulation DM-COP8/44P DM-COP8/40D DM-COP8/28D DM-COP8/20D DM-COP8/16D Optional Surface Mount Adapter Kits MHW-COP8/44P-Q DM-COP8/28D-SO DM-COP8/20D-SO DM-COP8/16D-SO Optional Programming Adapters COP8-PGMA-44Q 3.4 iceMASTER EVALUATION PROGRAMMING UNIT (EPU) The iceMASTER-COP8 EPU based, in-circuit simulation tool to support the feature family COP8 products. ...
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In addition, the EPU has programming capability, with added adapters, for programming the whole COP8 product family of OTP and EPROM products. The product includes the following features: • Non-real-time in-circuit simulation. Program overlay memory is PC resident; in- ...
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Installing the EPU Software You must have at least 1700 kilobytes of free disk space on your PC to install the EPU host software. To install this software type the following from the DOS command line: C:\>a:\install a: c: \epu-cop8 ...
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... COP8782, COP8781, COP8780 3.5 COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL KIT National Semiconductor offers a relocatable COP8 macro cross assembler, linker, librarian, and utility software development tool kit. Features are summarized as follows: • Basic and Feature Family instruction set by "device" type. • Nested macro capability. ...
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COP8-DEV-IBMA Assembler SDK on installable 3.5” PC format. Periodic upgrades and most recent version is available on National’s BBS and the Internet. 3.6 COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler ...
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... North/South Manufacturer America BP Microsystems US: Houston, TX (USA) 800-225-2102 www.bpmicro.com 713-688-4600 sales@bpmicro.com fax: 713-688-0920 bbx: 713-688-9283 Data I/O US: Redmond, WA (USA) 800-426-1045 www.data-io.com 206-881-6444 sales@data-io.com fax: 206-882-1043 techhelp@data-io.com bbs: 206-882-3211 CAN: 905-678-0761 fax: 905-678-7306 US: Fremont, CA (Taiwan) 510-623-8860 www.hilosystems.com.tw bbs: 510-623-0430 ICE Technology US: Henderson, NC (UK) 800-624-8949 www ...
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North/South Manufacturer America Systems General US: Milpitas, CA (Taiwan) 800-967-4776 408-263-6667 fax: 408-262-9220 bbs: 408-262-6438 Xeltek US: Sunnyvale, CA (USA) 408-524-1929 www.xeltek.com fax: 408-245-7084 info@xeltek.com bbs: 408-245-7082 3.8 AVAILABLE LITERATURE For more information, please see the COP8 Basic Family User's ...
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... Dial-A-Helper via a WorldWide Web Browser ftp://nscmicro.nsc.com 3.11 NATIONAL SEMICONDUCTOR ON THE WORLDWIDE WEB See us on the WorldWide Web at: http://www.national.com 3.12 CUSTOMER RESPONSE CENTER Complete product information and technical support is available from National's customer response centers. Please see back cover for telephone number in your area. ...
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This chapter describes several application examples using the COP8SAx7 family of microcontrollers. Design examples often include block diagrams and/or assembly code. Certain hardware design considerations are also presented. Topics covered in this chapter include the following: TESTING A REMOTE NORMALLY ...
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Some applications using remote normally open switches for sensors call for knowing whether the sensor is connected. Usually one cannot tell the difference between a normally open switch and a disconnected one. However, a 10k resistor is connected across the ...
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GCONF = 0D5 GPINS = 0D6 DPORT = 0DC CHECK: SBIT 0, GCONF SBIT 0, GDATA IFBIT 0, GPINS JP $1 SCLS: NOP SBIT 0, DPORT RBIT 1, DPORT JP CHECK $1 RBIT 0, GCONF IFBIT 0, GPINS JP OPEN ...
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A large number of off-the-shelf devices are directly compatible with the MICROWIRE/ PLUS interface. This allows direct interface of the COP888 microcontrollers with a large number of peripheral devices. The following sections provide examples of the MICROWIRE/PLUS interface. These examples ...
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Set the MSEL bit in the CNTRL register to enable MICROWIRE; G0 and G5 are configured as inputs and output. Reset bit 6 of the Port G con- figuration register to select Standard SK Clocking mode. ...
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It should be set at the typical or minimum specification of 10 ms. 3. The start bit on DI must be programmed as a “0” to “1” transition following a CS enable (“0” to “1”) when executing ...
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NMC93C06 EEPROM. .INCLD COP888.INC .SECT NMC, RAM NMCMEM: .DSB 5 SNDBUF = NMCMEM RDATL = NMCMEM+1 RDATH = NMCMEM+2 WDATL = ...
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NM93C06 ; ERAL: LD SNDBUF,#020 LD FLAGS,#0 JSR INIT RET ;This routine reads the contents of a NM93C06 register. The NM93C06 address is ;specified in the lower nibble of location “ADRESS.” The upper ...