C8051T606ZDB Silicon Laboratories Inc, C8051T606ZDB Datasheet - Page 85

• Manufacturer Part Number: C8051T606ZDB
• Description: CARD DAUGHTER QFN10 SOCKET
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T606ZDB

• Module/board Type: Socket Module - QFN
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T606
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1668

SFR Definition 17.3. EIE1: Extended Interrupt Enable 1
SFR Address = 0xE6
Name
Reset
Bit
7:6
Type
5
4
3
2
1
0
Bit
EWADC0 Enable Window Comparison ADC0 Interrupt.
Unused
ESMB0
ECP0R
EPCA0
EADC0
ECP0F
Name
R
7
0
Unused. Read = 00b; Write = Don’t Care.
Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 rising edge interrupt.
0: Disable CP0 rising edge interrupts.
1: Enable interrupt requests generated by the CP0RIF flag.
Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 falling edge interrupt.
0: Disable CP0 falling edge interrupts.
1: Enable interrupt requests generated by the CP0FIF flag.
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
R
6
0
ECP0R
R/W
5
0
ECP0F
R/W
Rev. 1.2
4
0
Function
C8051T600/1/2/3/4/5/6
EPCA0
R/W
3
0
EADC0
R/W
2
0
EWADC0
R/W
1
0
ESMB0
R/W
0
0
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