KSZ8851SNL-BBE-EVAL Micrel Inc, KSZ8851SNL-BBE-EVAL Datasheet - Page 8

• Manufacturer Part Number: KSZ8851SNL-BBE-EVAL
• Description: BOARD EVAL MAC/PHY FOR KSZ8851
• Manufacturer: Micrel Inc
• Series: LinkMD®r

Specifications of KSZ8851SNL-BBE-EVAL

• Design Resources: BeagleBoard Zippy2
• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8851SNL
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: SPI Interface, LinkMD Cable Diagnostics
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3602; KSZ8851SNL-BBE-EVL; ZIPPY2

Micrel, Inc.
KSZ8851SNL/SNLI
List of Figures
Figure 1. KSZ8851SNL/SNLI Functional Diagram.................................................................................................................. 1
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Figure 2. 32-Pin (5mm x 5mm) MLF
.................................................................................................................................. 10
Figure 3. Typical Straight Cable Connection ........................................................................................................................ 17
Figure 4. Typical Crossover Cable Connection .................................................................................................................... 18
Figure 5. Auto Negotiation and Parallel Operation ............................................................................................................... 19
Figure 6. SPI Interface to KSZ8851SNL ............................................................................................................................... 22
Figure 7. Internal I/O Register Read Timing ......................................................................................................................... 23
Figure 8. Internal I/O Register Write Timing ......................................................................................................................... 23
Figure 9. RXQ FIFO Read Timing......................................................................................................................................... 24
Figure 10. TXQ FIFO Write Timing ....................................................................................................................................... 24
Figure 11. Host TX Single Frame in Manual Enqueue Flow Diagram .................................................................................. 27
Figure 12. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................. 28
Figure 13. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram .................................................................. 30
Figure 14. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths....................................................... 32
Figure 15. SPI Interface Data Input Timing........................................................................................................................... 73
Figure 16. SPI Interface Data Output Timing........................................................................................................................ 73
Figure 17. Auto Negotiation Timing ...................................................................................................................................... 74
Figure 18. Reset Timing........................................................................................................................................................ 75
Figure 19. EEPROM Read Cycle Timing Diagram ............................................................................................................... 76
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Figure 20. 32-Pin (5mm x 5mm) MLF
(QFN per JDEC) Package ...................................................................................... 78
August 2009
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M9999-083109-2.0