ATAVRMC321 Atmel, ATAVRMC321 Datasheet - Page 149

• Manufacturer Part Number: ATAVRMC321
• Description: KIT EVAL MOTOR CTRL LOW COST
• Manufacturer: Atmel
• Series: AVR®r

Specifications of ATAVRMC321

• Main Purpose: Power Management, Motor Control
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATtinyx61
• Primary Attributes: 3-Ph BLDC, Brushed DC, Stepper Motor- Controller Board
• Secondary Attributes: Includes ATAVRMC300 Power Driver Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.6.1
15.6.2
15.7
2588E–AVR–08/10
ADC Noise Canceler
ADC Input Channels
ADC Voltage Reference
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the channel
selection. Since the next conversion has already started automatically, the next result will reflect
the previous channel selection. Subsequent conversions will reflect the new channel selection.
The voltage reference for the ADC (V
ended channels that exceed V
either V
version result after switching voltage reference source may be inaccurate, and the user is
advised to discard this result.
The ADC features a noise canceler that enables conversion during sleep mode. This reduces
noise induced from the CPU core and other I/O peripherals. The noise canceler can be used
with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure
should be used:
Note that the ADC will not automatically be turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-
ing such sleep modes to avoid excessive power consumption.
• When ADATE or ADEN is cleared.
• During conversion, minimum one ADC clock cycle after the trigger event.
• After a conversion, before the Interrupt Flag used as trigger source is cleared.
• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must
• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the
• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will
be selected and the ADC conversion complete interrupt must be enabled.
CPU has been halted.
wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another
interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be
executed, and an ADC Conversion Complete interrupt request will be generated when the
ADC conversion completes. The CPU will remain in active mode until a new sleep command
is executed.
CC
, or internal 1.1V / 2.56V voltage reference, or external AREF pin. The first ADC con-
REF
will result in codes close to 0x3FF. V
REF
) indicates the conversion range for the ADC. Single
REF
can be selected as
149