ATWEBDVK-02VOIP Atmel, ATWEBDVK-02VOIP Datasheet - Page 12

• Manufacturer Part Number: ATWEBDVK-02VOIP
• Description: KIT DEV TCP/IP AT89C51RD2 VOIP
• Manufacturer: Atmel
• Series: @Webr

Specifications of ATWEBDVK-02VOIP

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: AT89C51RD2
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 4-1.
12
AT89C51RD2/ED2
XTALA1
XTALA2
P2.0 - P2.7
P3.0 - P3.7
P4.0 - P4.7
P5.0 - P5.7
RST
Mnemonic
Pin Description (Continued)
PLCC44 VQFP44
24 - 31
13 - 19
11,
21
20
11
13
14
15
16
17
18
19
10
9
-
-
18 - 25
7 - 13
15
14
10
12
13
11
5,
3
5
7
8
9
4
-
-
Pin Number
10, 13, 16
PLCC68
63, 7, 8,
54, 55,
56, 58,
59, 61,
34, 39,
40, 41,
42, 43,
20, 24,
26, 44,
46, 50,
60, 62,
64, 65
45, 47
53, 57
29
49
48
34
39
40
41
42
43
45
47
30
63, 1, 4, 7
VQFP64
43, 44,
45, 47,
48, 50,
25, 28,
29, 30,
31, 32,
49, 51,
52, 62,
11, 15,
53, 54
34, 36
17,33,
35,39,
42, 46
20
38
37
25
28
29
30
31
32
34
36
21
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
Name and Function
P1.7: Input/Output:
CEX4: Capture/Compare External I/O for PCA module 4
MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master
controller.
XTALA 1: Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
XTALA 2: Output from the inverting oscillator amplifier
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below.
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to V
power-on reset using only an external capacitor to V
output when the hardware watchdog forces a system reset.
CC
. This pin is an
4235K–8051–05/08
SS
permits a