ATWEBDVK-02VOIP Atmel, ATWEBDVK-02VOIP Datasheet - Page 63

• Manufacturer Part Number: ATWEBDVK-02VOIP
• Description: KIT DEV TCP/IP AT89C51RD2 VOIP
• Manufacturer: Atmel
• Series: @Webr

Specifications of ATWEBDVK-02VOIP

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: AT89C51RD2
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

16. Serial Port Interface (SPI)
16.1
16.2
16.2.1
16.2.2
4235K–8051–05/08
Features
Signal Description
Master Output Slave Input (MOSI)
Master Input Slave Output (MISO)
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communica-
tion between the MCU and peripheral devices, including other MCUs.
Features of the SPI Module include the following:
Figure 16-1
peripherals. The bus is made of three wires connecting all the devices.
Figure 16-1. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel port to
control the four SS pins of the Slave devices.
This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI
line is used to transfer data in series from the Master to the Slave. Therefore, it is an output sig-
nal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO
line is used to transfer data in series from the Slave to the Master. Therefore, it is an output sig-
nal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
• Full-duplex, three-wire synchronous transfers
• Master or Slave operation
• Eight programmable Master clock rates
• Serial clock with programmable polarity and phase
• Master Mode fault error flag with MCU interrupt capability
• Write collision flag protection
shows a typical SPI bus configuration using one Master controller and many Slave
Master
Slave 4
MISO
MOSI
SCK
SS
0
1
2
3
VDD
Slave 3
AT89C51RD2/ED2
Slave 1
Slave 2
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