KSZ8041NL-EVAL Micrel Inc, KSZ8041NL-EVAL Datasheet - Page 16

• Manufacturer Part Number: KSZ8041NL-EVAL
• Description: BOARD EVALUATION FOR KSZ8041NL
• Manufacturer: Micrel Inc

Specifications of KSZ8041NL-EVAL

• Main Purpose: Interface, Ethernet PHY
• Embedded: No
• Utilized Ic / Part: KSZ8041NL
• Primary Attributes: Single Chip PHY, 10BASE-T/100BASE-TX
• Secondary Attributes: MII, RMII, HP Auto MDI, MDI-X Auto Polarity Correction
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1621

Micrel, Inc.
Pin Description – KSZ8041RNL
September 2010
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Pin Name
GND
VDDPLL_1.8
VDDA_3.3
RX-
RX+
TX-
TX+
XO
XI
REXT
MDIO
MDC
PHYAD0
PHYAD1
RXD1 /
PHYAD2
RXD0 /
DUPLEX
VDDIO_3.3
CRS_DV /
CONFIG2
REF_CLK
RX_ER /
ISO
INTRP
NC
TX_EN
Type
Ipu/O
Ipd/O
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Gnd
Opu
I/O
I/O
I/O
I/O
I/O
I/O
P
P
O
P
O
O
I
I
I
(1)
Pin Function
Ground
1.8V analog V
3.3V analog V
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041RNL reference schematics.
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset.
See “Strapping Options” section for details.
The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset.
See “Strapping Options” section for details.
RMII Mode:
Config Mode:
RMII Mode:
Config Mode:
3.3V digital V
RMII Mode:
Config Mode:
50MHz Clock Output
This pin provides the 50MHz RMII reference clock output to the MAC.
RMII Mode:
Config Mode:
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the
interrupt output to active low (default) or active high.
No connect
RMII Transmit Enable Input
DD
DD
DD
RMII Receive Data Output[1]
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
RMII Receive Data Output[0]
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
Carrier Sense/Receive Data Valid Output /
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
RMII Receive Error Output /
The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options” section for details.
16
(2)
(2)
/
/
M9999-090910-1.4
KSZ8041NL/RNL