ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 33

• Manufacturer Part Number: ATAVRSB202
• Description: KIT BATT MGMT FOR ATMEGA32HVB
• Manufacturer: Atmel

Specifications of ATAVRSB202

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.8.4
8042B–AVR–06/10
OSICSR – Oscillator Sampling Interface Control and Status Register
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, or clear the CLK-
PCE bit.
• Bit 1:0 – CLKPS[1:0]: Clock Prescaler Select Bit[1:0]
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 9-4 on page
ongoing VADC conversion.
Table 9-4.
Table 9-5.
Note:
• Bits 7:5, 3:2 – Reserved
These bits are reserved in the ATmega16HVB/32HVB and will always read as zero.
Bit
0x17 (0x37)
Read/Write
Initial Value
1. When changing Prescaler value, the VADC Prescaler will automatically change frequency of
the VADC clock and abort any ongoing conversion.
CLKPS1
CLKPS1
System Clock Prescaler Select
VADC Clock Prescaling
0
0
1
1
0
0
1
1
R
7
–
0
33. Note that writing to the System Clock Prescaler Select bits will abort any
R
6
–
0
R
5
–
0
(1)
OSISEL0
R/W
CLKPS0
CLKPS0
4
0
0
1
0
1
0
1
0
1
ATmega16HVB/32HVB
R
3
–
0
R
2
–
0
VADC Division Factor
Clock Division Factor
OSIST
R
1
0
OSIEN
8
4
2
1
1
2
4
8
R/W
0
0
OSICSR
33