ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 61
ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.2.7
8042B–AVR–06/10
PCMSK0 – Pin Change Mask Register 0
• Bit 7:0 – PCINT[11:4]: Pin Change Enable Mask 15:8
These bits select whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[11:4] is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT[11:4] is cleared, pin change interrupt on the corresponding I/O pin
is disabled.
• Bits 7:4 – Reserved
These bits are reserved in the ATmega16HVB/32HVB, and will always read as zero.
• Bit 3:0 – PCINT[3:0]: Pin Change Enable Mask 3:0
Each PCINT[3:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[3:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[3:0] is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
Bit
(0x6B)
Read/Write
Initial Value
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
PCINT3
R/W
ATmega16HVB/32HVB
3
0
PCINT2
R/W
2
0
PCINT1
R/W
1
0
PCINT0
R/W
0
0
PCMSK0
61
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