AD9520-4/PCBZ Analog Devices Inc, AD9520-4/PCBZ Datasheet - Page 11

• Manufacturer Part Number: AD9520-4/PCBZ
• Description: BOARD EVAL FOR AD9520-4
• Manufacturer: Analog Devices Inc

Specifications of AD9520-4/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9520-4
• Primary Attributes: 1.4 ~ 1.8 GHz Output Frequency
• Secondary Attributes: Accepts CMOS, LVDS, or LVPECL References Up to 250 MHz
• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Clock Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9520-0, AD9520-2, AD9520-2
• Silicon Family Name: AD9520-X
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVPECL ABSOLUTE PHASE NOISE
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 1.8 GHz; OUTPUT = 1.8 GHz
VCO = 1.625 GHz; OUTPUT = 1.625 GHz
VCO = 1.45 GHz; OUTPUT = 1.45 GHz
VCO = 1.475 GHz; LVPECL = 245.76 MHz; PLL LBW = 39 kHz
VCO = 1.475 GHz; LVPECL = 122.88 MHz; PLL LBW = 39 kHz
VCO = 1.475 GHz; LVPECL = 61.44 MHz; PLL LBW = 39 kHz
VCO = 1.555 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.8 kHz
VCO = 1.474 GHz; LVPECL = 122.88 MHz; PLL LBW = 1.9 kHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
Min
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Typ
−54
−84
−108
−128
−143
−148
−58
−87
−111
−130
−144
−148
−62
−91
−115
−133
−143
−148
Min
Min
Max
Typ
440
360
Typ
109
269
114
263
146
291
Max
Max
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unit
f
f
S
S
Unit
f
f
f
f
f
f
S
S
S
S
S
S
rms
rms
rms
rms
rms
rms
rms
rms
Test Conditions/Comments
Internal VCO; direct-to-LVPECL output and for
loop bandwidths < 1 kHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
jittery, so a narrower PLL loop bandwidth
is used; reference = 10.0 MHz; R = 20
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
AD9520-4