AD9520-4/PCBZ Analog Devices Inc, AD9520-4/PCBZ Datasheet - Page 24

BOARD EVAL FOR AD9520-4

AD9520-4/PCBZ

Manufacturer Part Number
AD9520-4/PCBZ
Description
BOARD EVAL FOR AD9520-4
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD9520-4/PCBZ

Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9520-4
Primary Attributes
1.4 ~ 1.8 GHz Output Frequency
Secondary Attributes
Accepts CMOS, LVDS, or LVPECL References Up to 250 MHz
Silicon Manufacturer
Analog Devices
Application Sub Type
PLL Clock Synthesizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9520-0, AD9520-2, AD9520-2
Silicon Family Name
AD9520-X
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9520-4
Figure 24. Internal VCO Phase Noise (Absolute) Direct-to-LVPECL @ 1625 MHz
Figure 25. Internal VCO Phase Noise (Absolute) Direct-to-LVPECL @ 1800 MHz
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–160
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
Figure 26. Additive (Residual) Phase Noise CLK-to-LVPECL @
1k
1k
10
100
10k
10k
245.76 MHz, Divide-by-1
1k
100k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
100k
1M
1M
1M
10M
10M
10M
100M
100M
100M
Rev. 0 | Page 24 of 84
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
–110
–120
–130
–140
–150
–160
–170
Figure 27. Additive (Residual) Phase Noise, CLK-to-LVPECL @
Figure 28. Additive (Residual) Phase Noise CLK-to-LVPECL @
Figure 29. Additive (Residual) Phase Noise, CLK-to-CMOS @
10
10
10
100
100
100
1k
1k
1k
1600 MHz, Divide-by-1
200 MHz, Divide-by-5
50 MHz, Divide-by-20
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
10k
10k
100k
100k
100k
1M
1M
1M
10M
10M
10M
100M
100M
100M

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