AD9520-4/PCBZ Analog Devices Inc, AD9520-4/PCBZ Datasheet - Page 70
![BOARD EVAL FOR AD9520-4](/photos/9/8/90843/analog_devices_ad9520-4_pcbz_sml.jpg)
AD9520-4/PCBZ
Manufacturer Part Number
AD9520-4/PCBZ
Description
BOARD EVAL FOR AD9520-4
Manufacturer
Analog Devices Inc
Specifications of AD9520-4/PCBZ
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9520-4
Primary Attributes
1.4 ~ 1.8 GHz Output Frequency
Secondary Attributes
Accepts CMOS, LVDS, or LVPECL References Up to 250 MHz
Silicon Manufacturer
Analog Devices
Application Sub Type
PLL Clock Synthesizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9520-0, AD9520-2, AD9520-2
Silicon Family Name
AD9520-X
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Reg.
Addr
(Hex) Bit(s) Name
017
018
018
018
018
018
AD9520-4
[1:0] Antibacklash
[7]
[6:5] Lock detect
[4]
[3]
[2:1] VCO calibration
pulse width
Enable CMOS
reference input
dc offset
counter
Digital lock
detect window
Disable digital
lock detect
divider
Description
[7]
1
1
1
1
1
1
1
1
1
1
1
1
[1]
0
0
1
1
Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost.
[7] = 0; disable dc offset (default).
[7] = 1; enable dc offset.
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates
a locked condition.
[6]
0
0
1
1
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time,
the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock
threshold.
[4] = 0; high range (default).
[4] = 1; low range.
Digital lock detect operation.
[3] = 0; normal lock detect operation (default).
[3] = 1; disable lock detect.
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock (see the
VCO Calibration section for the recommended setting of the VCO calibration divider based on the PFD rate.)
[2]
0
0
1
1
[6] [5] [4]
1
1
1
1
1
1
1
1
1
1
1
1
[0]
0
1
0
1
[5]
0
1
0
1
[1]
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
VCO Calibration Clock Divider
2
4
8
16 (default)
Antibacklash Pulse Width (ns)
2.9 (default)
1.3
6.0
2.9
PFD Cycles to Determine Lock
5 (default)
16
64
255
1
1
1
1
0
0
0
0
1
1
1
1
[3]
0
0
1
1
0
0
1
1
0
0
1
1
Rev. 0 | Page 70 of 84
[2]
0
1
0
1
0
1
0
1
0
1
0
1
Level or
Dynamic
Signal
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Signal at STATUS Pin
Unselected reference to PLL (not available when in
differential mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential
mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency) .
(DLD) AND (Status of selected reference) AND (status of VCO) .
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
DLD (active low).
Holdover active (active low).
LD pin comparator output (active low).