CDB42448 Cirrus Logic Inc, CDB42448 Datasheet - Page 22

• Manufacturer Part Number: CDB42448
• Description: BOARD EVAL FOR CS42448 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42448

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42448
• Primary Attributes: 24-Bit, 192 kHz, 6 ADCs: 102dB Dynamic Range, 8 DACs: 105dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), I2C, and SPI Interface, Popguard® Technology
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• For Use With/related Products: CS42448
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1151

5.6
NOTE: To avoid contention with the FPGA, set the clock direction for the FPGA appropriately: FPGA->DAC and
FPGA->ADC in register 03h and 07h must be set to ‘1’b.
22
Reserved
7
BYPASS CONTROL (ADDRESS 06H)
5.5.5
5.5.6
5.6.1
5.6.2
Default = 0
0 - Left-Justified
1 - I
Function:
Default = 0
0 - Enabled
1 - Disabled
Function:
Default = 1
0 - Enable
1 - Disable
Function:
Default = 1
0 - Enable
1 - Disable
Function:
²
Selects either I
µs whenever this bit changes.
Enables/disables the external MCLK output buffer on the MCLK bus (see Figure 6 on page 13).
This bit toggles a control line for the data buffer external to the FPGA to route the DSP Data directly
to the DAC (see Figure 7 on page 14). The inverted signal controls active low buffers internal to the
FPGA that routes the FPGA data to the DAC. Refer to Figure 4 on page 11.
This bit toggles a control line for the external data buffer to route the ADC Data directly to the DSP
(see Figure 7 on page 14). The inverted signal controls active low buffers external to the FPGA that
S
DSPDATA
RMCK MASTERS MCLK BUS (RMCK_MASTER)
DSP DATA ROUTE TO DAC (DSPDATA->DAC)
ADC SDOUT DATA ROUTE TO DSP (SDOUT->DSP)
LEFT-JUSTIFIED OR I
->DAC
6
²
SDOUT->DSP
S or Left Justified interface format for the CS8416. Pin 6 (RST bit) is held low for 300
5
²
S INTERFACE FORMAT (I
CS5341
->AUX
4
DAC->DSP
3
²
S/LJ)
ADC->DSP
2
DSP->DAC
1
CDB42448
DSP->ADC
DS648DB2
0