CDB5376 Cirrus Logic Inc, CDB5376 Datasheet - Page 79

• Manufacturer Part Number: CDB5376
• Description: EVALUATION BOARD FOR CS5376
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5376

• Main Purpose: Seismic Evaluation System
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS3301A, CS3302A, CS4373A, CS5372A, CS5376A
• Primary Attributes: Quad Digital Filter
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Processor To Be Evaluated: CS330x, CS4373A, CS537x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1778

Modified SINC2 filter to correct gain and
timing errors
Corrected gain error of 333 SPS output rate
Modified SINC3 filter for new low band-
width rates.
Added minimum phase FIR coefficients
Corrected IIR2/IIR3 channels 2, 3, 4 bug
DS612F4
Corrected SINC2 decimate by 2 gain error
which affected 4000 SPS operation. Also mod-
ified SINC2 decimate by 16 output timing to
match output of other SINC2 rates. Previous
SINC2 decimate by 16 output was one sample
later than expected.
SINC architecture was modified to correct gain
error in SINC2 decimate by 12 by moving dec-
imate by 3 stage into SINC3.
Newly supported output word rates are 200,
125, 100, 50, 40, 25, 20, 10, 5, 1 SPS. Older low
bandwidth rates of 120, 60, 30, 15, 7.5 SPS
were removed. No changes to 4000, 2000,
1000, 500, 333, 250 SPS rates for backwards
compatibility to CS5376 revision A/B.
Minimum phase FIR1 coefficient set 1 and
FIR2 coefficient set 1 are newly available as se-
lections for the SPI and EEPROM 'Write ROM
Coefficients' command.
When selecting IIR2 or IIR3 output, data from
channels 2, 3, and 4 were corrupted. IIR2 and
IIR3 now operate correctly for these channels.
Corrected IIR2 coefficient DC offset
Removed gain scale factor from 'Write TBS
ROM' command
Removed watchdog timer
Set GPIO11 as tri-state when EEPROM boot
completed
Modified Test Bit Stream (TBS) to disable
loopback when TBS disabled.
IIR2 coefficient sets 0, 1, and 3 did not perfect-
ly cancel DC due to coefficient b20, b21, b22
mismatch. New b21 IIR2 coefficients correct
this offset error.
TBS data was previously scaled during config-
uration by a data word following the 'Write
TBS ROM' command. Added a new TBSGAIN
register (0x2B, replacing WD_CFG) that scales
the TBS amplitude and can be modified during
normal operation.
The watchdog timer was removed. Replaced
WD_CFG register (0x2B) with TBSGAIN reg-
ister.
After stand-alone boot from EEPROM,
GPIO11 (acting as EEPROM chip select) was
previously driven high. This pin now tri-states
with an internal pull-up to hold it high.
If TBS loopback mode was enabled, the exter-
nal MDATA inputs were disconnected from the
SINC filter even if the TBS was disabled. Now
when the TBS is disabled, loopback mode is
automatically disabled also.
CS5376A
79