HIP4080A/81AEVALZ Intersil, HIP4080A/81AEVALZ Datasheet - Page 4

• Manufacturer Part Number: HIP4080A/81AEVALZ
• Description: DEMO BOARD FOR HIP4081A
• Manufacturer: Intersil

Specifications of HIP4080A/81AEVALZ

• Main Purpose: Power Management, H Bridge Driver (Internal FET)
• Utilized Ic / Part: HIP4080A, HIP4081A
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: HIP4080A/81AEVAL; HIP4080A/81AEVAL; Q2670719

The input sensitivity of the DIS and HEN input pins are best
described as “enhanced TTL” levels. Inputs which fall below
1.0V or above 2.5V are recognized, respectively, as low level
or high level inputs. The IN+ and IN- comparator inputs have
a common mode input voltage range of 1.0V to V
whereas the offset voltage is less than 5mV. For more
information on the comparator specifications, see Intersil
Data Sheet HIP4080A, FN3658.
Propagation Delay Control
Propagation delay control is a major feature of the
HIP4080A. Two identical sub-circuits within the IC delay the
commutation of the power MOSFET gate turn-on signals for
both A and B sides of the H-bridge. The gate turn-off signals
are not delayed. Propagation delays related to the level-
translation function (see section on“Level-Translation” on
page 4) cause both upper on/off propagation delays to be
longer than the lower on/off propagation delays. Four delay
sub-circuits are needed to fully balance the H-bridge delays,
two for upper delay control and two for lower gate control.
Users can tailor the low side to high side commutation delay
times by placing a resistor from the HDEL pin to the V
Similarly, a resistor connected from LDEL to V
high side to low side commutation delay times of the lower
power switches. The HDEL resistor controls both upper
commutation delays and the LDEL resistor controls the
lower commutation delays. Each of the resistors sets a
current which is inversely proportional to the created delay.
The delay is added to the falling edge of the “off” pulse
associated with the MOSFET which is being commutated off.
When the delay is complete, the “on” pulse is initiated. This
has the effect of “delaying” the commanded on pulse by the
amount set by the delay, thereby creating dead-time.
Proper choice of resistor values connected from HDEL and
LDEL to V
commutation dead times whether commutating high to low
or low to high. Values for the resistors ranging from 10kΩ to
200kΩ are recommended. Figure 5 shows the delays
obtainable as a function of the resistor values used.
IN+ >
IN-
X
X
1
0
1
0
X = DON’T CARE
U/V
X
TABLE 1. INPUT LOGIC TRUTH TABLE
1
0
0
0
0
SS
provides a means for matching the
DIS
1
X
0
0
0
0
HEN
X
X
1 = HIGH/ON
1
1
0
0
4
ALO
0
0
0
1
0
1
AHO
0
0
1
0
0
0
0 = LOW/OFF
BLO
SS
0
0
1
0
1
0
controls the
Application Note 9404
DD
BHO
/1.5V,
SS
0
0
0
1
0
0
pin.
Level-Translation
The lower power MOSFET gate drive signals from the
propagation delay and control circuits go to amplification
circuits which are described in more detail under the section
“Driver Circuits” on page 5. The upper power MOSFET gate
drive signals are directed first to the Level-Translation
circuits before going to the upper power MOSFET “Driver
Circuits”.
The Level-Translation circuit communicate “on” and “off”
pulses from the Propagation Delay sub-circuit to the upper
logic and gate drive sub-circuits which “float” at the potential
of the upper power MOSFET source connections. This
voltage can be as much as 85V when the bias supply
voltage is only 10V (the sum of the bias supply voltage and
bus voltages must not exceed 95VDC).
In order to minimize power dissipation in the level-shifter
circuit, it is important to minimize the width of the pulses
translated because the power dissipation is proportional to
the product of switching frequency and pulse energy in
joules. The pulse energy in turn is equal to the product of the
bus voltage magnitude, translation pulse current and
translation pulse duration. To provide a reliable, noise free
pulse requires a nominal current pulse magnitude of
approximately 3mA. The translated pulses are then “latched”
to maintain the “on” or “off” state until another
level-translation pulse comes along to set the latch to the
opposite state. Very reliable operation can be obtained with
pulse widths of approximately 80ns. At a switching
frequency of even 1.0MHz, with an 80VDC bus potential, the
power developed by the level-translation circuit will be less
than 0.08W.
FIGURE 5. MINIMUM DEAD-TIME vs DEL RESISTANCE
150
120
90
60
30
0
10
50
HDEL/LDEL RESISTANCE (kΩ)
100
150
200
December 11, 2007
AN9404.3
250