CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet - Page 10

• Manufacturer Part Number: CLINK3V48BT-133
• Description: BOARD EVAL FOR DS90CR485, 486
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-133

• Main Purpose: Interface, SerDes (Serializer / De-Serializer)
• Embedded: No
• Utilized Ic / Part: DS90CR485, DS90CR486
• Primary Attributes: Serializes 48 LVCMOS/LVTTL to 8 LVDS, 66 ~ 133 MHz
• Secondary Attributes: Transmits over 2 Meter 3M MDR LVDS Cable
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Design Tip Overview
Channel Link are robust, easy-to-use SerDes, but to get the best performance from your interconnect design, it’s a good idea to review your
design for best practices.
•
requirements.
•
data sampling. Keep supply noise under 100 mV peak-to-peak on PLL V
•
the transmitter serial output.
•
termination resistor is close to the receiver input.
•
receiver TTL outputs RxOUT if driving long PCB traces and/or more than 1-2 loads.
Pair-to-Pair Skew: Large skew between LVDS clock and data pairs can cause mis-sampling of data. Make sure pair-to-pair skew meets RSKM
Power Supply Noise: Excessive supply noise, especially on the PLL supply, can add jitter to the transmitter serial output and affect the receiver
Transmit Clock: Minimize excessive cycle-to-cycle jitter on the transmit clock TxCLKIN in the range of 200 kHz - 3 MHz which can add jitter to
Serial Bus: Should follow LVDS PCB layout and backplane recommendations, using proper termination, avoiding long stubs, and assuring the
Parallel Bus: The parallel TTL signals should meet setup and hold times and should be free from excessive overshoot/undershoot. Buffer
10
Design Review
Check Your Design for High Performance
CC
pins.
Ω