CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet - Page 5

• Manufacturer Part Number: CLINK3V48BT-133
• Description: BOARD EVAL FOR DS90CR485, 486
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-133

• Main Purpose: Interface, SerDes (Serializer / De-Serializer)
• Embedded: No
• Utilized Ic / Part: DS90CR485, DS90CR486
• Primary Attributes: Serializes 48 LVCMOS/LVTTL to 8 LVDS, 66 ~ 133 MHz
• Secondary Attributes: Transmits over 2 Meter 3M MDR LVDS Cable
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Printed Circuit Board (PCB) Recommen-
dations
•
ground, power, and TTL signals).
•
data
•
noise is less than 100 mV peak-to-peak.
•
are recommended for LVDS signals. Edge-coupled
microstrip, edge-coupled stripline, or broadside-coupled
stripline differential traces may be used. These traces
should be closely-coupled (i.e. “s” should be minimized)
to ensure coupled noise will appear as common-mode
(which is rejected by the receiver). This has the added
benefit that closely-coupled lines that are excited with
odd-mode transmission tend to radiate less electromag-
netic energy.
•
avoiding influences that cause imbalances within the
pair (see diagram at right). Minimize skew within the
pair. Maintain “balance.”
•
LVDS deserializer inputs open (floating) – internal
failsafe will pull the input to a valid state.
•
termination resistor value should match the differential
impedance of the transmission line. 100-Ohm is a typi-
cal value for point-to-point applications. It is better err
with too large a termination resistor than too small.
•
them at least “3s” or “2w” away—whichever is larger.
This will help to prevent them from coupling onto the
LVDS lines.
These are just a few common practices that should
be followed when designing PCBs for LVDS signaling.
General application guidelines are available in the LVDS
Owner’s Manual and other documents at lvds.national.
com.
Use at least 4 PCB board layers (LVDS signals,
Minimize pair-to-pair skew between LVDS clock and
Use proper power supply bypassing such that PLL V
Controlled impedance differential traces of 100 Ohms
Treat the entire LVDS clock+data bus as one signal,
Tie unused TTL inputs high or low. Leave unused
Termination of the LVDS signals is required. The
Isolate TTL/CMOS signals from LVDS signals, placing
CC
PCB Recommendations