CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet - Page 14

• Manufacturer Part Number: CLINK3V48BT-133
• Description: BOARD EVAL FOR DS90CR485, 486
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-133

• Main Purpose: Interface, SerDes (Serializer / De-Serializer)
• Embedded: No
• Utilized Ic / Part: DS90CR485, DS90CR486
• Primary Attributes: Serializes 48 LVCMOS/LVTTL to 8 LVDS, 66 ~ 133 MHz
• Secondary Attributes: Transmits over 2 Meter 3M MDR LVDS Cable
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Deskew
The 48-bit Channel Link deskew function compensates for fixed pair-to-pair skew such as the fixed skew in cables, connectors, and PCB traces.
Deskew operation is fundamentally different in the DS90CR482/484 versus the DS90CR486. With the DS90CR482/484, deskew operation is initi-
ated by the serializer. The serializer DS_OPT pin is held low for 50 us and the serializer sends a deskew pattern to the deserializer. The deserial-
izer recognizes this pattern and performs the deskew operation if its DESKEW pin is high.
Using the DS90CR486, however, deskew is initiated by the DS90CR486 deserializer and not via the serializer. For the DS90CR486 to deskew
properly, it must receive switching data on its inputs either during power up or when toggling the DS90CR486 DESKEW pin.
Differences between DS90CR482/484 and DS90CR486 deskew operation are:
• DS90CR482/484 deskew is controlled by toggling the DS90CR481/483/485 serializer DS_OPT pin. DS90CR486 deskew is controlled by toggling
the DS90CR486 deserializer DESKEW pin.
• The DS90CR482/484 deskew function works up to 80 MHz. The DS90CR486 deskew works over its entire operating clock range.
• The DS90CR482/484 deskew works only in DC balance mode. The DS90CR486 works in both DC balance and non-DC-balance modes.
• The DS90CR482/484 deskew up to ± 1 LVDS data bit time (UI). The DS90CR486 deskews up to ± 200 ps. If interconnect skew exceeds these
values, the additional skew will degrade noise margins and must be subtracted from RSKM.
• The DS90CR486 performs deskew automatically upon power up.
During deskew operation, the DS90CR486 requires a switching pattern for at least 4096 clock cycles on all LVDS data inputs to optimize deskew
calibration. In a valid deskew switching pattern, each data line has at least one LVDS edge transition per clock cycle. This switching pat-
tern can be generated by the system—or the DS90CR481/483/485 transmitters can generate a valid deskew pattern automatically using the
DS90CR481/483/485 transmitter DS_OPT pin.
Deskew should be performed at system start up and whenever the cable is replaced. Once deskew is performed, it does not need to be repeated
as long as the pair-to-pair system skew remains within the RSKM budget. A well-designed system has enough RSKM margin to accommodate
the very small skew changes due to temperature, voltage and age. For example, after a system starts up, it deskews the cable. As long as the
cable is not replaced with a different cable, deskew is normally not repeated.
Toggle 481/3/5 DS_OPT
DS90CR482 or 484
Deskew Complete
(DC Balance Mode ≤ 80 Mhz Only
are powered up and locked
pin LOW at least 4 clocks
DESKEW pin must be HIGH)
14
Verify Sync
Ensure Tx & Rx
Channel Link Operation
DS90CR48x Deskew
Bring control pins (incl. DESKEW) high
(make sure DESKEW pin is HIGH)
≥ 4096 Clock Cycles
Start sending switching pattern
Power Up Tx & Rx
Deskew Complete
Deskew training duration
†
This pattern can be a random data generated by the system or the deskew pattern
generated by a DS90CR481/3/5 receivers when its DS_OPT pin is pulled LOW.
Wait 20 ms
Switching pattern has at least one LVDS edge transition per clock cycle.
PLL lock time
During Power Up
†
DS90CR486
(make sure DESKEW pin is high)
≥ 4096 Clock Cycles
Start sending switching pattern
Toggle 486 Deskew
After Power Up
Deskew Complete
pin LOW for at least 4 clocks
Deskew training duration
†