CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet - Page 8

• Manufacturer Part Number: CLINK3V48BT-133
• Description: BOARD EVAL FOR DS90CR485, 486
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-133

• Main Purpose: Interface, SerDes (Serializer / De-Serializer)
• Embedded: No
• Utilized Ic / Part: DS90CR485, DS90CR486
• Primary Attributes: Serializes 48 LVCMOS/LVTTL to 8 LVDS, 66 ~ 133 MHz
• Secondary Attributes: Transmits over 2 Meter 3M MDR LVDS Cable
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LVDS Termination
LVDS termination is required. Choose the termination resistor value RL to match the loaded differential impedance of the transmission line. In
point-to-point applications, the termination value is typically 100 Ohms. Place a termination resistors as close as possible to the receiver inputs or
end of the transmission lines.
Input Over- and Undershoot
Excessive over- and undershoot injects noise into the power supply and PLL, decreasing link margin. Reduce FPGA output drive to ensure over-
and undershoot are minimized and < 300 mV above and below power/ground. Terminate LVTTL lines if necessary.
Transmitter Input Clock Jitter (TxCLKIN)
For Channel Link SerDes, cycle-to-cycle jitter is more critical than long term jitter. Although Channel Link SerDes employ jitter filters and have
been characterized with cycle-to-cycle input clock impulses up to ± 300 ps, cycle-to-cycle input clock jitter should be minimized so that the serial-
izer LVDS clock cycle-to-cycle jitter is less than 100 ps.
Spread Spectrum Clocking
Spread spectrum clocking can be used with Channel Link SerDes. Down spectrum is preferred over center or up spectrum since this increases tim-
ing margins. Spread spectrum of 1-2% with a carrier frequency < 200 kHz (50 - 100 kHz is common) is recommended to ensure the PLL tracking.
Receiver Output Clock (RxCLKOUT)
The receiver output clock is an LVCMOS output whose rising edge is aligned to the middle of the receiver output data RxOUT. The subsequent
ASIC/FPGA device should latch in RxOUT data meeting the ASIC/FPGAs input setup and hold times. Output jitter for RxCLKOUT is not specified on
the datasheet since it depends on the jitter of the incoming data and the TxCLKIN clock source.
Interoperability of Channel Link Chipsets
Any 21-bit Channel Link serializer can be used with any 21-bit Channel Link deserializer over the devices’ overlapping operating frequency ranges.
The same is true for 28- and 48- bit chipsets. The power supplies of the serializer and deserializer do not need to be the same, in fact, 5V and
3.3V Channel Link serializers and deserializers may be used on different ends of the link.
Unused TTL Inputs
Unused LVTTL inputs should be tied high or low. Many Channel Link devices (check devices) have internal pull down devices to bias unused pins.
These internal impedances tend to be in the 200 kOhm range and may be overridden with lower value pull up resistors if desired.
Floating LVDS Receiver Inputs & Failsafe
In the event that the Channel Link receiver is disconnected from the backplane/cable, the internal failsafe circuitry is designed to reject a certain
amount of differential noise (about 10 mV) from being interpreted as data or clock. This seems like a very small threshold, but balanced, closely-
coupled LVDS lines tend to pick up noise as common mode—not differential. Additional failsafe biasing can be implemented externally (see
application note AN-1194 and LVDS Owner’s Manual sections 4.6.2-3) at the expense of two additional resistors. Receiver data and clock output
status when its LVDS inputs are floating is shown in the table at the end of this design guide.
Receiver Output Drive
To minimize EMI and power consumption, Channel Link receiver output drive is on the order of a few milliamps. This is typically sufficient to drive
1-2 LVTTL/LVCMOS loads. If more loads or long traces will be driven, especially at higher clock speeds, a logic buffer is recommended. Note that
depending on actual configuration (number of loads, stub lengths, segment distances, etc.), the receiver output bus may need to be treated as a
transmission line and proper LVTTL/LVCMOS termination techniques employed.
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Design Guidelines
Inputs & Outputs