HW-V5-ML523-FXT-UNI-G-J Xilinx Inc, HW-V5-ML523-FXT-UNI-G-J Datasheet - Page 29
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HW-V5-ML523-FXT-UNI-G-J
Manufacturer Part Number
HW-V5-ML523-FXT-UNI-G-J
Description
BOARD EVAL FOR VIRTEX-5
Manufacturer
Xilinx Inc
Series
Virtex™ -5r
Datasheet
1.HW-V5-ML523-FXT-UNI-G-J.pdf
(36 pages)
Specifications of HW-V5-ML523-FXT-UNI-G-J
Main Purpose
Interface, Transceiver, RocketIO
Utilized Ic / Part
Virtex™-5 FPGA
For Use With
HW-XGI-SCLK-G - MODULE SUPER CLOCKHW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-NQSL-G - NQSL NELCO QUAD SERIAL LOOPHW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-SDRAM - EXPANSION MOD SDRAM BERG-SDRAM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
ML52x User Guide
UG225 (v2.1) August 4, 2010
21. RS-232 Port Pins
22. Xilinx Generic Interface (XGI)
R
The RS-232 port pin connections to the DUT are as shown in
in DTE mode as shown in
Table 18: RS-232 Port Pins
X-Ref Target - Figure 4
The XGI is an expansion interface for plug-in modules (for example, the SuperClock
module) and provides the user access to the I/O pins listed in the tables below.
Table 19
converted to an alphanumeric column and row format.
Table 19: Top View of PCB
Pin Name
RXD
TXD
CTS
RTS
Row
1
2
3
4
5
(spanning multiple pages) shows the schematic pinout of the XGI interface
Virtex-5
U1
Direction
OUT
OUT
IN
IN
F
1
3
5
7
9
RXD
TXD
RTS
CTS
J113
Figure 4: RS-232 Pins in DTE Mode
www.xilinx.com
Figure
Column
R1OUT
R2OUT
Port Name
10
T1IN
T2IN
E
2
4
6
8
R1OUT
R2OUT
4.
T1IN
T2IN
U3
J135
RS232
D
1
2
3
4
5
ML521
G14
H13
G16
G15
J136
C
1
2
3
4
5
Column
Table
Pin 3
Pin 7
Pin 2
Pin 8
J3
ML523
B
UG225_04_112807
1
3
5
7
9
L16
L15
L20
L21
DB9
18. The pins are set up
J118
Detailed Description
10
A
2
4
6
8
ML525
N25
P17
P18
P25
29