CDB5345 Cirrus Logic Inc, CDB5345 Datasheet - Page 31

• Manufacturer Part Number: CDB5345
• Description: EVALUATION BOARD FOR CS5345
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5345

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Inputs Per Adc: 6 Single Ended
• Power (typ) @ Conditions: 400mW @ 5 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS5345
• Description/function: Audio A/D
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS5345
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1780

DS658F2
6. REGISTER DESCRIPTION
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
PART3
Freeze
7
7
Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1110b (0Eh), and the remaining
bits (3 through 0) indicate the device revision as shown in
Power Control - Address 02h
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in
Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
Table
Reserved
PART2
5.
6
6
Reserved
PART1
Gain[5:0]
Gain[5:0]
Name
Mute
5
5
REV[2:0]
001
010
011
Table 4. Device Revision
Table 5. Freeze-able Bits
Reserved
PART0
4
4
Register
04h
07h
08h
PDN_MIC
REV3
3
3
Revision
Table 4
B, C0
C1
A
PDN_ADC
below.
REV2
2
2
Bit(s)
5:0
5:0
2
Reserved
REV1
1
1
CS5345
REV0
PDN
0
0
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