CDB5364 Cirrus Logic Inc, CDB5364 Datasheet - Page 24

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CDB5364

Manufacturer Part Number
CDB5364
Description
EVALUATION BOARD FOR CS5364
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB5364

Number Of Adc's
1
Number Of Bits
24
Sampling Rate (per Second)
192k
Data Interface
I²C, SPI™
Inputs Per Adc
4 Differential
Power (typ) @ Conditions
365mW @ 192kSPS
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS5364
Description/function
Audio A/D
Operating Supply Voltage
3.3 V
Product
Audio Modules
For Use With/related Products
CS5364
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
24
4.6.3 Master Mode Clock Dividers
4.6.4 Slave Mode Audio Clocking With Auto-Detect
MCLK
External
MCLK
pin
bit
Figure 13
cluding the significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode).
In Slave Mode, CS5364 auto-detects speed mode, which eliminates the need to configure M1 and M0 when
changing among speed modes. The external MCLK is subject to clock dividers as set by the clock divider
pins in Stand-Alone Mode or the clock divider bits in Control Port Mode. The CS5364 compares the divided-
down, internal MCLK to the incoming LRCK/FS and sets the speed mode based on the MCLK/LRCK ratio
as shown in
pin
bit
CLKMODE
CLKMODE
CLKMODE
CLKMODE
÷ 1.5
0/1
÷ 1
MCLK DIVIDERS
÷ 1.5
shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, in-
0/1
÷ 1
Figure
MCLK DIVIDERS
MDIV1
MDIV
0/1
÷ 1
÷ 2
MDIV1
MDIV
14.
0/1
÷ 1
÷ 2
MDIV0
0/1
n/a
Figure 14. Slave Mode Auto-Detect Speed
÷ 1
÷ 2
MDIV0
Figure 13. Master Mode Clock Dividers
0/1
n/a
÷ 1
÷ 2
Internal
MCLK
÷LRCK
LRCK
SAMPLE RATE DIVIDERS
÷ 256
÷ 128
÷ 64
÷ 4
÷ 2
÷ 1
Double
Single
Speed
Speed
Speed
Double
Single
Speed
Speed
Speed
Quad
Quad
256
128
M1
64
00
01
10
SPEED MODE
00
01
10
M0
Double-Speed
Single-Speed
Quad-Speed
CS5364
SCLK
DS625F4
LRCK/ FS

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