CDB5364 Cirrus Logic Inc, CDB5364 Datasheet - Page 30

• Manufacturer Part Number: CDB5364
• Description: EVALUATION BOARD FOR CS5364
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5364

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: I²C, SPI™
• Inputs Per Adc: 4 Differential
• Power (typ) @ Conditions: 365mW @ 192kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5364
• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5364
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

30
4.13
4.13.1 SPI Mode
.
Control Port Operation
The Control Port is used to read and write the internal device registers. It supports two industry standard
formats, I²C and SPI. The part is in I²C format by default. SPI Mode is selected if there is ever a high-to-low
transition on the AD0/CS pin after the RST pin has been restored high.
In Control Port Mode, all features of the CS5364 are available. Four multi-use configuration pins become
software pins that support the I²C or SPI bus protocol. To initiate Control Port Mode, a controller that sup-
ports I²C or SPI must be used to enable the internal register functionality. This is done by setting the
CP-EN bit (Bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins
are ignored, and the internal register settings determine the operating modes of the part.
In SPI Mode, CS is the CS5364 chip select signal; CCLK is the control port bit clock (input into the CS5364
from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a controller.
Data is clocked in on the rising edge of CCLK and is supplied on the falling edge of CCLK.
To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be
1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits
form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated.
The next eight bits are the data that will be placed into the register designated by the MAP. During writes,
the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 kΩ resistor, if
desired.
There is a MAP auto-increment capability, which is enabled by the INCR bit in the MAP register. If INCR is
a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-
increment after each byte is read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle that fin-
ishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not, as
desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear
consecutively
C C L K
CS
C D IN
C D O U T
ADDRESS
MAP = Memory Address Pointer, 8 bits, MSB first
1001111
C H I P
High Impedance
R/W
M A P
MSB
b y te 1
Figure 16. SPI Format
DATA
b y te n
LSB
A D D R E S S
C H IP
1001111
R/W
MSB
LSB MSB
LSB
CS5364
DS625F4