CDB5364 Cirrus Logic Inc, CDB5364 Datasheet - Page 34

• Manufacturer Part Number: CDB5364
• Description: EVALUATION BOARD FOR CS5364
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5364

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: I²C, SPI™
• Inputs Per Adc: 4 Differential
• Power (typ) @ Conditions: 365mW @ 192kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5364
• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5364
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

34
5.6
5.7
5.8
5.9
5.10
RESERVED
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
04h (HPF) High-Pass Filter Register
Default: 0x00, all high-pass filters enabled.
The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each channel.
These filters are used to perform DC offset calibration, a procedure that is detailed in
on page
05h Reserved
06h (PDN) Power Down Register
Default: 0x00 - everything powered up
The Power Down Register is used as needed to reduce the chip’s power consumption.
Bit[7] RESERVED
Bit[6] RESERVED
Bit[5] PDN-BG When set, this bit powers-down the bandgap reference.
Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscillator core is
shut down, and no clock is supplied to the chip. If the chip is running off an externally supplied clock at the
MCLK pin, it is also prevented from clocking the device internally.
Bit[1:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial data outputs
are forced to all zeroes.
07h Reserved
08h (MUTE) Mute Control Register
Default: 0x00, no channels are muted.
The Mute Control Register is used to mute or unmute the serial audio data output of individual channels.
When a bit is set, that channel’s serial data is muted by forcing the output to all zeroes.
RESERVED RESERVED RESERVED RESERVED
RESERVED RESERVED RESERVED RESERVED
29.
7
7
7
7
7
-
-
RESERVED
6
6
6
6
6
-
-
PDN-BG
5
5
5
5
5
-
-
PDN-OSC
4
4
4
4
4
-
-
RESERVED RESERVED
MUTE4
HPF4
3
3
3
3
3
-
-
MUTE3
HPF3
2
2
2
2
2
-
-
MUTE2
PDN43
HPF2
1
“DC Offset Control”
1
1
1
1
-
-
CS5364
MUTE1
DS625F4
PDN21
HPF1
0
0
0
0
0
-
-