ADC122S706EB/NOPB National Semiconductor, ADC122S706EB/NOPB Datasheet - Page 17

• Manufacturer Part Number: ADC122S706EB/NOPB
• Description: BOARD EVAL FOR ADC122S706
• Manufacturer: National Semiconductor

Specifications of ADC122S706EB/NOPB

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 25mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC122S706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC122S706EB

Functional Description
The ADC122S706 is a dual 12-bit, simultaneous sampling
Analog-to-Digital (A/D) converter. The converter is based on
a successive-approximation register (SAR) architecture
where the differential nature of the analog inputs is main-
tained from the internal track-and-hold circuits throughout the
A/D converter. The analog inputs on both channels are sam-
pled simultaneously to preserve their relative phase informa-
tion to each other. The architecture and process allow the
ADC122S706 to acquire and convert dual analog signals at
sample rates up to 1 MSPS while consuming very little power.
The ADC122S706 operates from independent analog and
digital supplies. The analog supply (V
to 5.5V and the digital supply (V
V
ternal reference can be any voltage between 1V and V
value of the reference voltage determines the range of the
analog input, while the reference input current depends upon
the conversion rate.
Analog inputs are presented at the inputs of Channel A and
Channel B. Upon initiation of a conversion, the differential in-
put at these pins is sampled on the internal capacitor array.
The inputs are disconnected from the internal circuitry while
a conversion is in progress.
The ADC122S706 requires an external clock. The duty cycle
of the clock is essentially unimportant, provided the minimum
clock high and low times are met. The minimum clock fre-
quency is set by internal capacitor leakage. Each conversion
requires 16 SCLK cycles to complete. If less than 12 bits of
conversion data are required, CS can be brought high at any
point during the conversion.
The ADC122S706 offers dual high-speed serial data outputs
that are binary 2's complement and are compatible with sev-
eral standards, such as SPI™, QSPI™, MICROWIRE™, and
many common DSP serial interfaces. Channel A's conversion
result is outputted on D
sult is outputted on D
C122S706 an excellent replacement for systems using two
distinct ADCs in a simultaneous sampling application. The
serial clock (SCLK) and chip select bar (CS) are shared by
both channels. The digital conversion of channel A and B is
clocked out by the SCLK input and is provided serially, most
significant bit first, at D
digital data that is provided at D
conversion currently in progress. With CS held low after the
conversion is complete, the ADC122S706 continuously con-
verts the analog inputs. For lower power consumption, a
single serial data output mode is externally selectable. This
feature makes the ADC122S706 an excellent replacement for
two independent ADCs that are part of a daisy chain config-
uration.
1.0 REFERENCE INPUT
The externally supplied reference voltage sets the analog in-
put range. The ADC122S706 will operate with a reference
voltage in the range of 1V to V
Operation with a reference voltage below 1V is also possible
with slightly diminished performance. As the reference volt-
age (V
voltages is reduced. Assuming a proper common-mode input
voltage, the differential peak-to-peak input range is limited to
twice V
value of V
(LSB). The size of one LSB is equal to twice the reference
voltage divided by 4096. When the LSB size goes below the
A
. The ADC122S706 utilizes an external reference. The ex-
REF
REF
) is reduced, the range of acceptable analog input
REF
. See Section 2.3 for more details. Reducing the
also reduces the size of the least significant bit
OUTA
OUTB
OUTA
while Channel B's conversion re-
. This feature makes the AD-
and D
A
OUTA
.
D
) can range from 2.7V to
OUTB
and D
A
) can range from 4.5V
, respectively. The
OUTB
is that of the
A
. The
17
noise floor of the ADC122S706, the noise will span an in-
creasing number of codes and overall performance will suffer.
For example, dynamic signals will have their SNR degrade,
while D.C. measurements will have their code uncertainty in-
crease. Since the noise is Gaussian in nature, the effects of
this noise can be reduced by averaging the results of a num-
ber of consecutive conversions.
Additionally, since offset and gain errors are specified in LSB,
any offset and/or gain errors inherent in the A/D converter will
increase in terms of LSB size as the reference voltage is re-
duced.
The reference input and the analog inputs are connected to
the capacitor array through a switch matrix when the input is
sampled. Hence, the current requirements at the reference
and at the analog inputs are a series of transient spikes that
occur at a frequency dependent on the operating sample rate
of the ADC122S706.
The reference current changes only slightly with temperature.
See the curves, “Reference Current vs. SCLK Frequency”
and “Reference Current vs. Temperature” in the Typical Per-
formance Curves section for additional details.
2.0 ANALOG SIGNAL INPUTS
The ADC122S706 has dual differential inputs where the ef-
fective input voltage that is digitized is CHA+ minus CHA−
(DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case
with all differential input A/D converters, operation with a fully
differential input signal or voltage will provide better perfor-
mance than with a single-ended input. However, the
ADC122S706 can be presented with a single-ended input.
The current required to recharge the input sampling capacitor
will cause voltage spikes at the + and − inputs. Do not try to
filter out these noise spikes. Rather, ensure that the transient
settles out during the acquisition period (three SCLK cycles
after the fall of CS).
2.1 Differential Input Operation
With a fully differential input voltage or signal, a positive full
scale output code (0111 1111 1111b or 7FFh) will be obtained
when DIFFINA or DIFFINB is greater than or equal to V
1.5 LSB. A negative full scale code (1000 0000 0000b or
800h) will be obtained when DIFFINA or DIFFINB is greater
than or equal to −V
and linearity errors, which will affect the exact differential input
voltage that will determine any given output code. Figure 8
shows the ADC122S706 being driven by a full-scale differen-
tial source.
FIGURE 8. Differential Input
REF
+ 0.5 LSB. This ignores gain, offset
30017180
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REF
−