ADC122S706EB/NOPB National Semiconductor, ADC122S706EB/NOPB Datasheet - Page 18

• Manufacturer Part Number: ADC122S706EB/NOPB
• Description: BOARD EVAL FOR ADC122S706
• Manufacturer: National Semiconductor

Specifications of ADC122S706EB/NOPB

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 25mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC122S706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC122S706EB

www.national.com
2.2 Single-Ended Input Operation
For single-ended operation, the non-inverting inputs of the
ADC122S706 can be driven with a signal that has a maximum
to minimum value range that is equal to or less than twice the
reference voltage. The inverting inputs should be biased at a
stable voltage that is halfway between these maximum and
minimum values. In order to utilize the entire dynamic range
of the ADC122S706, the reference voltage is limited at V
2. This allows the non-inverting inputs the maximum swing
range of ground to V
ing driven by a full-scale single-ended source.
Since the design of the ADC122S706 is optimized for a dif-
ferential input, the performance degrades slightly when driven
with a single-ended input. Linearity characteristics such as
INL and DNL typically degrade by 0.1 LSB and dynamic char-
acteristics such as SINAD typically degrades by 2 dB. Note
that single-ended operation should only be used if the perfor-
mance degradation (compared with differential operation) is
acceptable.
2.3 Input Common Mode Voltage
The allowable input common mode voltage (V
pends upon the supply and reference voltages used for the
ADC122S706. The ranges of V
and Figure 11. Equations for calculating the minimum and
maximum common mode voltages for differential and single-
ended operation are shown in Table 1.
FIGURE 10. V
FIGURE 9. Single-Ended Input
CM
range for Differential Input operation
A
. Figure 9 shows the ADC122S706 be-
CM
are depicted in Figure 10
30017181
CM
30017161
) range de-
A
/
18
3.0 SERIAL DIGITAL INTERFACE
The ADC122S706 communicates via a synchronous serial
interface as shown in the Timing Diagram section. CS, chip
select, initiates conversions and frames the serial data trans-
fers. SCLK (serial clock) controls both the conversion process
and the timing of the serial data. D
serial data output pins, where the conversion results of Chan-
nel A and Channel B are sent as serial data streams, MSB
first.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. The ADC122S706's data output pins
are in a high impedance state when CS is high and are active
when CS is low; thus CS acts as an output enable. A timing
diagram for a single conversion is shown in Figure 1.
During the first three cycles of SCLK, the ADC122S706 is in
acquisition mode (t
next twelve SCLK cycles (t
plished and the data is clocked out. SCLK falling edges one
through four clock out leading zeros while falling edges five
through sixteen clock out the conversion result, MSB first. If
there is more than one conversion in a frame (continuous
conversion mode), the ADC122S706 will re-enter acquisition
mode on the falling edge of SCLK after the N*16th rising edge
of SCLK and re-enter the conversion mode on the N*16+4th
falling edge of SCLK as shown in Figure 3. "N" is an integer
value.
The ADC122S706 can enter acquisition mode under three
different conditions. The first condition involves CS going low
(asserted) with SCLK high. In this case, the ADC122S706
enters acquisition mode on the first falling edge of SCLK after
CS is asserted. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC122S706 automati-
cally enters acquisition mode and the falling edge of CS is
seen as the first falling edge of SCLK. In the third condition,
CS and SCLK go low simultaneously and the ADC122S706
enters acquisition mode. While there is no timing restriction
with respect to the falling edges of CS and the falling edge of
SCLK, see Figure 6 for setup and hold time requirements for
the falling edge of CS with respect to the rising edge of SCLK.
Differential
Single-Ended
Input Signal
FIGURE 11. V
TABLE 1. Allowable V
CM
ACQ
range for single-ended operation
Minimum V
), tracking the input voltage. For the
V
REF
V
REF
CONV
/ 2
), the conversion is accom-
CM
OUTA
CM
Range
Maximum V
and D
V
A
V
A
− V
− V
30017162
OUTB
REF
REF
/ 2
are the
CM