ADC122S706EB/NOPB National Semiconductor, ADC122S706EB/NOPB Datasheet - Page 20

• Manufacturer Part Number: ADC122S706EB/NOPB
• Description: BOARD EVAL FOR ADC122S706
• Manufacturer: National Semiconductor

Specifications of ADC122S706EB/NOPB

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 25mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC122S706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC122S706EB

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4.2 Burst Mode Operation
Normal operation of the ADC122S706 requires the SCLK fre-
quency to be sixteen times the sample rate and the CS rate
to be the same as the sample rate. However, in order to min-
imize power consumption in applications requiring sample
rates below 500 kSPS, the ADC122S706 should be run with
an SCLK frequency of 16 MHz and a CS rate as slow as the
system
ADC122S706 is operating in burst mode. The ADC122S706
enters into power down mode at the end of each conversion,
minimizing power consumption. This causes the converter to
spend the longest possible time in power down mode. Since
power consumption scales directly with conversion rate, min-
imizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the sys-
tem.
4.3 Single DOUT mode
With the DUAL pin connected to a logic low level, the AD-
C122S706 is operating in single DOUT mode. In single DOUT
mode, the conversion result of Channel A and Channel B are
both output on D
causes the maximum conversion rate to be reduced to 500k-
SPS while operating with an SCLK frequency of 16MHz. This
is a result of the conversion window changing from 16 clock
cycles to 32 clock cycles to receive the conversion result of
Channel A and Channel B. Since the conversion of Channel
A and Channel B are still performed simultaneously, the AD-
C122S706 still enters a power down state on the 16th falling
edge of SCLK. The increased time spent in power down mode
causes the power consumption of the ADC122S706 to reduce
nearly by a factor of two. See the Power Supply Characteris-
tics Table for more details.
5.0 POWER SUPPLY CONSIDERATIONS AND PCB
LAYOUT
For best performance, care should be taken with the physical
layout of the printed circuit board. This is especially true with
a low reference voltage or when the conversion rate is high.
At high clock rates there is less time for settling, so it is im-
portant that any noise settles out before the conversion be-
gins.
5.1 Analog and Digital Power Supplies
Any ADC architecture is sensitive to spikes on the power sup-
ply, reference, and ground pins. These spikes may originate
from switching power supplies, digital logic, high power de-
vices, and other sources. Power to the ADC122S706 should
be clean and well bypassed. A 0.1 µF ceramic bypass ca-
pacitor and a 1 µF to 10 µF capacitor should be used to
bypass the ADC122S706 supply, with the 0.1 µF capacitor
placed as close to the ADC122S706 package as possible.
Since the ADC122S706 has both an analog and a digital sup-
ply pin, the user has three options. The first option is to tie the
analog and digital supply pins together and power them with
the same power supply. This is the most cost effective way of
powering the ADC122S706 but it is also the least ideal. As
stated previously, noise from the digital supply pin can couple
into the analog supply pin and adversely affect performance.
The other two options involve the user powering the analog
and digital supply pins with separate supply voltages. These
supply voltages can have the same amplitude or they can be
different. The only design constraint is that the digital supply
voltage be less than the analog supply voltage. This is not
requires.
OUTA
When
(see Figure 2). Operating in this mode
this
is
accomplished,
the
20
usually a problem since many applications prefer a digital in-
terface of 3V while operating the analog section of the AD-
C122S706 at 5V. Operating the digital supply pin at 3V as
apposed to 5V offers two advantages. It lowers the power
consumption of the ADC122S706 and it decreases the noise
created by charging and discharging the capacitance of the
digital interface pins.
5.2 Voltage Reference
The reference source must have a low output impedance and
needs to be bypassed with a minimum capacitor value of 0.1
µF. A larger capacitor value of 1 µF to 10 µF placed in parallel
with the 0.1 µF is preferred. While the ADC122S706 draws
very little current from the reference on average, there are
higher instantaneous current spikes at the reference input.
The reference input of the ADC122S706, like all A/D convert-
ers, does not reject noise or voltage variations. Keep this in
mind if the reference voltage is derived from the power supply.
Any noise and/or ripple from the supply that is not rejected by
the external reference circuitry will appear in the digital re-
sults. The use of an active reference source is recommended.
The LM4040 and LM4050 shunt reference families and the
LM4132 and LM4140 series reference families are excellent
choices for a reference source.
5.3 PCB Layout
Capacitive coupling between the noisy digital circuitry and the
sensitive analog circuitry can lead to poor performance. The
solution is to keep the analog circuitry separated from the
digital circuitry and the clock line as short as possible. Digital
circuits create substantial supply and ground current tran-
sients. The logic noise generated could have significant im-
pact upon system noise performance. To avoid performance
degradation of the ADC122S706 due to supply noise, avoid
using the same supply for the VA and VREF of the AD-
C122S706 that is used for digital circuity on the board.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. However, to maximize accuracy in high
resolution systems, avoid crossing analog and digital lines al-
together. It is important to keep clock lines as short as possi-
ble and isolated from ALL other lines, including other digital
lines. In addition, the clock line should also be treated as a
transmission line and be properly terminated. The analog in-
put should be isolated from noisy signal traces to avoid cou-
pling of spurious signals into the input. Any external
component (e.g., a filter capacitor) connected between the
converter's input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the
ground plane.
A single, uniform ground plane and the use of split power
planes are recommended. The power planes should be lo-
cated within the same board layer. All analog circuitry (input
amplifiers, filters, reference components, etc.) should be
placed over the analog power plane. All digital circuitry and I/
O lines should be placed over the digital power plane. Fur-
thermore, the GND pin on the ADC122S706 and all the
components in the reference circuitry and input signal chain
that are connected to ground should be connected to the
ground plane at a quiet point. Avoid connecting these points
too close to the ground point of a microprocessor, microcon-
troller, digital signal processor, or other high power digital
device.