ADC122S706EB/NOPB National Semiconductor, ADC122S706EB/NOPB Datasheet - Page 19

• Manufacturer Part Number: ADC122S706EB/NOPB
• Description: BOARD EVAL FOR ADC122S706
• Manufacturer: National Semiconductor

Specifications of ADC122S706EB/NOPB

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 25mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC122S706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC122S706EB

3.1 CS Input
The CS (chip select bar) is an active low input that is TTL and
CMOS compatible. The ADC122S706 is in conversion mode
when CS is low and power-down mode when CS is high. As
a result, CS frames the conversion window. The falling edge
of CS marks the beginning of a conversion and the rising edge
of CS marks the end of a conversion window. Multiple con-
versions can occur within a given conversion frame with each
conversion requiring sixteen SCLK cycles. This is referred to
as continuous conversion mode and is shown in Figure 3 of
the Timing Diagram section.
Proper operation requires that the fall of CS not occur simul-
taneously with a rising edge of SCLK. If the fall of CS occurs
during the rising edge of SCLK, the data might be clocked out
one bit early. Whether or not the data is clocked out early
depends upon how close the CS transition is to the SCLK
transition, the device temperature, and characteristics of the
individual device. To ensure that the MSB is always clocked
out at a given time (the 5th falling edge of SCLK), it is essential
that the fall of CS always meet the timing requirement speci-
fied in the Timing Specification table.
3.2 SCLK Input
The SCLK (serial clock) serves two purposes in the AD-
C122S706. It is used by the ADC as the conversion clock and
it is used as the serial clock to output the conversion results.
This SCLK input is CMOS compatible. Internal settling time
requirements limit the maximum clock frequency while inter-
nal capacitor leakage limits the minimum clock frequency.
The ADC122S706 offers guaranteed performance with the
clock rates indicated in the electrical table.
3.3 Data Output(s)
The ADC122S706 enables system designers two options for
receiving converted data from the ADC122S706. Data can be
received from separate data output pins (D
or from a single data output line. These options are controlled
by the digital input pin DUAL. With the DUAL pin set to a logic
high level, the dual high-speed serial outputs are enabled.
Channel A's conversion result is outputted on D
Channel B's conversion result is outputted on D
DUAL pin set to a logic low level, the conversion result of
Channel A and Channel B is outputted on D
result of Channel A being outputted before the result of Chan-
nel B. The D
condition. See Figure 1 and Figure 2 in the Timing Diagram
section for more details on DUAL and SINGLE DOUT mode.
The output data format of the ADC122S706 is two’s comple-
ment, as shown in Table 2. This table indicates the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, linearity errors, or noise. Each
data bit is output on the falling edge of SCLK.
While data is output on the falling edges of SCLK, receiving
systems have the option of capturing the data on the subse-
−V
V
Analog Input
0V − 1.5 LSB
(+IN) − (−IN)
REF
REF
+ 0.5 LSB
− 0.5 LSB
TABLE 2. Ideal Output Code vs. Input Voltage
− 1.5 LSB 0111 1111 1111
+ 0.5 LSB 1000 0000 0000
OUTB
pin is in a high impedance state during this
0000 0000 0001
0000 0000 0000
1111 1111 1111
Binary Output
Complement
2's
Hex Code
Comp.
FFF
7FF
001
000
800
2's
OUTA
OUTA
OUTB
and D
Dec Code
OUTA
Comp.
, with the
−2048
. With the
2047
2's
−1
1
0
OUTB
while
)
19
quent rising or falling edge of SCLK. The maximum specifi-
cation for t
is provided for two power supply ranges. If the system is op-
erating at the maximum clock frequency of 16MHz and a V
supply voltage of 3V, it would be necessary for the receiver
to capture data on the subsequent falling edge of SCLK in
order to guarantee performance over the entire temperature
range. Operating at a V
frequency less than 10MHz allows data to be captured on ei-
ther edge of SCLK. If a receiving system is going to capture
data on the subsequent falling edge of SCLK, it is important
to make sure that the minimum hold time after an SCLK falling
edge (t
cess times.
D
rising edge of CS. If CS is raised prior to the 16th falling edge
of SCLK, the current conversion is aborted and D
into its high impedance state. A new conversion will begin
when CS is taken LOW.
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC122S706:
−40°C
+4.5V
+2.7V
1V
8 MHz
V
4.0 POWER CONSUMPTION
The architecture, design, and fabrication process allow the
ADC122S706 to operate at conversion rates up to 1 MSPS
while consuming very little power. The ADC122S706 con-
sumes the least amount of power while operating in power
down mode. For applications where power consumption is
critical, the ADC122S706 should be operated in power down
mode as often as the application will tolerate. To further re-
duce power consumption, stop the SCLK while CS is high.
4.1 Short Cycling
Short cycling refers to the process of halting a conversion af-
ter the last needed bit is outputted. Short cycling can be used
to lower the power consumption in those applications that do
not need a full 12-bit resolution, or where an analog signal is
being monitored until some condition occurs. For example, it
may not be necessary to use the full 12-bit resolution of the
ADC122S706 as long as the signal being monitored is within
certain limits. In some circumstances, the conversion could
be terminated after the first few bits. This will lower power
consumption in the converter since the ADC122S706 spends
more time in power down mode and less time in the conver-
sion mode.
Short cycling is accomplished by pulling CS high after the last
required bit is received from the ADC122S706 output. This is
possible because the ADC122S706 places the latest con-
verted data bit on D
conversion result are needed, for example, the conversion
can be terminated by pulling CS high after the 8th bit has been
clocked out.
CM
OUT
≤
: See Section 2.3
is enabled on the falling edge of CS and disabled on the
V
≤
≤
≤
DH
REF
≤
V
V
T
) is acceptable. See Figure 5 for D
f
SCLK
A
D
A
DA
≤
≤
≤
≤
V
(D
+5.5V
V
+105°C
A
≤
A
OUT
16 MHz
OUT
access time after an SCLK falling edge)
as it is generated. If only 8-bits of the
D
supply voltage of 5V or an SCLK
OUT
hold and ac-
www.national.com
OUT
will go
D