HI7190EVAL Intersil, HI7190EVAL Datasheet - Page 16

• Manufacturer Part Number: HI7190EVAL
• Description: EVALUATION PLATFORM HI7190
• Manufacturer: Intersil

Specifications of HI7190EVAL

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 15mW @ 200kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI7190
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

first SCLK transition output is delayed 29 OSC
the next rising OSC
stalls high for 28 OSC
completed SCLK will again transition eight times and stall
high. This sequence will repeat continuously while CS is
active.
The extra OSC
inactive state is a one clock cycle latency required to
properly sample the CS input. Note that the normal stall at
byte boundaries is 28 OSC
to rising edge stall period of 32 OSC
The affects of CS on the I/O are different for self-clocking
mode (MODE = 1) than for external mode (MODE = 0). For
external clocking mode CS inactive disables the I/O state
machine, effectively freezing the state of the I/O cycle. That
is, an I/O cycle can be interrupted using chip select and the
HI7190 will continue with that I/O cycle when re-enabled via
CS. SCLK can continue toggling while CS is inactive. If CS
goes inactive during an I/O cycle, it is up to the user to
ensure that the state of SCLK is identical when reactivating
CS as to what it was when CS went inactive. For read
operations in external clocking mode, the output will go
three-state immediately upon deactivation of CS.
For self-clocking mode (MODE = 1), the affects of CS are
different. If CS transitions high (inactive) during the period
when data is being transferred (any non stall time) the HI7190
will complete the data transfer to the byte boundary. That is,
once SCLK begins the eight transition sequence, it will always
complete the eight cycles. If CS remains inactive after the byte
has been transferred it will be sampled and SCLK will remain
stalled high indefinitely. If CS has returned to active low before
the data byte transfer period is completed the HI7190 acts as
if CS was active during the entire transfer period.
It is important to realize that the user can interrupt a data
transfer on byte boundaries. That is, if the Instruction
Register calls for a 3 byte transfer and CS is inactive after
only one byte has been transferred, the HI7190, when
reactivated, will continue with the remaining two bytes before
looking for the next Instruction Register write cycle.
Note that the outputs will NOT go three-state immediately upon
CS inactive for read operations in self-clocking mode. In the
case of CS going inactive during a read cycle the outputs
remain driving until after the last data bit is transferred. In the
OSC
SCLK
CS
1
1
cycle required when coming out of the CS
1
. SCLK transitions eight times and then
1
cycles. After this stall period is
1
cycles thus giving a SCLK rising
16
29
FIGURE 12. SCLK OUTPUT IN SELF-CLOCKING MODE
1
cycles.
33
1
cycles from
37
HI7190
41
case of CS inactive during the clock stall time it takes 1 OSC
cycle plus prop delay (Max) for the outputs to be disabled.
I/O Port Pin Descriptions
The serial I/O port is a bidirectional port which is used to
read the data register and read or write the control register
and calibration registers. The port contains two data lines, a
synchronous clock, and a status flag. Figure 11 shows a
diagram of the serial interface lines.
SDO - Serial Data out. Data is read from this line using those
protocols with separate lines for transmitting and receiving
data. An example of such a standard is the Motorola Serial
Peripheral Interface (SPI) using the 68HC05 and 68HC11
family of microcontrollers, or other similar processors. In the
case of using bidirectional data transfer on SDIO, SDO does
not output data and is set in a high impedance state.
SDIO - Serial Data in or out. Data is always written to the
device on this line. However, this line can be used as a
bidirectional data line. This is done by properly setting up the
Control Register. Bidirectional data transfer on this line can
be used with Intel standard serial interfaces (SSR, Mode 0)
in MCS51 and MCS96 family of microcontrollers, or other
similar processors.
SCLK - Serial clock. The serial clock pin is used to
synchronize data to and from the HI7190 and to run the port
state machines. In Synchronous External Clock Mode, SCLK
is configured as an input, is supplied by the user, and can
run up to a 5MHz rate. In Synchronous Self Clocking Mode,
SCLK is configured as an output and runs at OSC
CS - Chip select. This signal is an active low input that allows
more than one device on the same serial communication lines.
The SDO and SDIO will go to a high impedance state when this
signal is high. If driven high during any communication cycle,
that cycle will be suspended until CS reactivation. Chip select
can be tied low in systems that maintain control of SCLK.
45
BIDIRECTIONAL DATA
FIGURE 11. HI7190 SERIAL INTERFACE
DEVICE STATUS
CLOCK MODE
PORT CLOCK
CHIP SELECT
89
DATA OUT
121
SDO
SDIO
SCLK
CS
DRDY
MODE
HI7190
125
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June 27, 2006
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FN3612.10
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