HI7190EVAL Intersil, HI7190EVAL Datasheet - Page 22

• Manufacturer Part Number: HI7190EVAL
• Description: EVALUATION PLATFORM HI7190
• Manufacturer: Intersil

Specifications of HI7190EVAL

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 15mW @ 200kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI7190
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

result in conversion X + 1 data overwriting conversion X
results. For example, with f
read cycle must start within 1/2000 - 128(1/10
after DRDY went low.
2) The Data Output Register read cycle for conversion X
must be completed within 2(1/f
initially goes active low. If the read cycle for conversion X is
not complete within this time the results of conversion X + 1
are lost and results from conversion X + 2 are now stored in
the data output word buffer.
Completing the Data Output Register read cycle inactivates
the DRDY interrupt. If the one word data output buffer is full
when this read is complete this data will be immediately
transferred to the Data Output Register and a new DRDY
interrupt will be issued after the minimum DRDY pulse high
time is met.
Writing the Control Register
If data is written to byte 2 and/or byte 1 of the Control
Register the DRDY output is taken high and the device re-
calibrates if written to a calibration mode. This action is taken
because it is assumed that by writing byte 2 or byte 1 that
the user either reprogrammed the filter or changed modes of
the part. However, if a single data byte is written to byte 0, it
is assumed that the gain has NOT been changed. It is up to
the user to re-calibrate the HI7190 after the gain has been
changed by this method. It is recommended that the entire
Control Register be written to when changing the selected
gain. This ensures that the part is re-calibrated before the
DRDY signal goes low indicating valid data is available.
Offset Calibration Register
The Offset Calibration Register is a 24-bit register containing
the offset correction factor. This register is indeterminate on
power-up but will contain a Self Calibration correction value
after a RESET has been applied.
The Offset Calibration Register holds the value that corrects
the filter output data to all 0’s when the analog input is 0V.
MSB
O23
O15
O7
15
7
O22
O14
O6
22
14
6
O21
O13
O5
21
13
5
O20
O12
O4
20
12
4
BYTE 2
BYTE 1
BYTE 0
OSC
22
N
= 10MHz, f
O19
)-1440(1/f
O11
O3
19
11
3
O18
O10
O2
18
10
2
OSC
N
= 2kHz, the
6
) after DRDY
) = 487μs
O17
O1
O9
17
9
1
O16
LSB
O8
O0
16
8
HI7190
Positive Full Scale Calibration Register
The Positive Full Scale Calibration Register is a 24-bit
register containing the Positive Full Scale correction
coefficient. This coefficient is used to determine the positive
gain slope factor. This register is indeterminate on power-up
but will contain a Self Calibration correction coefficient after
a RESET has been applied.
Negative Full Scale Calibration Register
The Negative Full Scale Calibration Register is a 24-bit
register containing the Negative Full Scale correction
coefficient. This coefficient is used to determine the negative
gain slope factor. This register is indeterminate on power-up
but will contain a Self Calibration correction coefficient after
a RESET has been applied.
MSB
MSB
P23
P15
N23
N15
P7
N7
15
15
7
7
P22
P14
N22
N14
N6
P6
22
14
22
14
6
6
N21
N13
P21
P13
N5
21
13
P5
21
13
5
5
P20
P12
N20
N12
P4
N4
20
12
20
12
4
4
BYTE 2
BYTE 1
BYTE 0
BYTE 2
BYTE 1
BYTE 0
P19
P11
N19
N11
N3
19
P3
19
11
11
3
3
N18
N10
P18
P10
P2
N2
18
10
18
10
2
2
P17
N17
P9
P1
N9
N1
17
17
9
1
9
1
June 27, 2006
FN3612.10
LSB
LSB
N16
P16
N8
N0
16
P8
P0
16
8
8