ADC14DS105KARB/NOPB National Semiconductor, ADC14DS105KARB/NOPB Datasheet - Page 20

• Manufacturer Part Number: ADC14DS105KARB/NOPB
• Description: BOARD EVAL FOR ADC14DS105KARB
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14DS105KARB/NOPB

• Design Resources: ADC14DS105KARB Ref Design
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 1W @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14DS105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14DS105KARB

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2.1.2 Driving the Analog Inputs
The V
internal sample-and-hold circuit which consists of an analog
switch followed by a switched-capacitor amplifier.
One short-coming of using a transformer to achieve the sin-
gle-ended to differential conversion is that most RF trans-
formers have poor low frequency performance. A differential
amplifier can be used to drive the analog inputs for low fre-
quency applications. The amplifier must be fast enough to
settle from the charging glitches on the analog input resulting
from the sample-and-hold operation before the clock goes
high and the sample is passed to the ADC core.
2.1.3 Input Common Mode Voltage
The input common mode voltage, V
of 1.4V to 1.6V and be a value such that the peak excursions
of the analog signal do not go more negative than ground or
more positive than 2.6V. It is recommended to use V
7,9) as the input common mode voltage.
2.2 Reference Pins
The ADC14DS1050 is designed to operate with an internal or
external 1.2V reference. The internal 1.2 Volt reference is the
default condition when no external reference input is applied
to the V
V
V
V
V
CM
CM
CM
CM
IN
+ and the V
REF
V
− V
− V
V
+ V
+ V
CM
IN
pin. If a voltage is applied to the V
+
REF
REF
REF
REF
/2
/4
/4
/2
IN
− inputs of the ADC14DS105 have an
V
V
V
V
CM
CM
CM
CM
V
V
+ V
+ V
− V
− V
FIGURE 8. High Input Frequency Transformer Drive Circuit
FIGURE 7. Low Input Frequency Transformer Drive Circuit
CM
IN
CM
−
REF
REF
REF
REF
, should be in the range
/2
/4
/4
/2
TABLE 1. Input to Output Relationship
REF
00 0000 0000 0000
01 0000 0000 0000
10 0000 0000 0000
11 0000 0000 0000
11 1111 1111 1111
CMO
pin, then
Binary Output
(pins
20
Figure 7 and Figure 8 show examples of single-ended to dif-
ferential conversion circuits. The circuit in Figure 7 works well
for input frequencies up to approximately 70MHz, while the
circuit in Figure 8 works well above 70MHz.
that voltage is used for the reference. The V
always be bypassed to ground with a 0.1 µF capacitor close
to the reference input pin.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects of
noise currents in the ground path.
The Reference Bypass Pins (V
nels A and B are made available for bypass purposes. These
pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 1 µF capacitor placed very
close to the pin to minimize stray inductance. A 0.1 µF ca-
pacitor should be placed between V
the pins as possible, and a 1 µF capacitor should be placed
in parallel. This configuration is shown in Figure 9. It is nec-
essary to avoid reference oscillation, which could result in
reduced SFDR and/or SNR. V
use as a temperature stable 1.5V reference. The remaining
pins should not be loaded.
Smaller capacitor values than those specified will allow faster
recovery from the power down mode, but may result in de-
2’s Complement Output
10 0000 0000 0000
11 0000 0000 0000
00 0000 0000 0000
01 0000 0000 0000
01 1111 1111 1111
20211282
20211283
CMO
RP
, V
may be loaded to 1mA for
CMO
RP
Negative Full-Scale
Positive Full-Scale
and V
, and V
Mid-Scale
REF
RN
RN
as close to
pin should
) for chan-