ADC14DS105KARB/NOPB National Semiconductor, ADC14DS105KARB/NOPB Datasheet - Page 6
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ADC14DS105KARB/NOPB
Manufacturer Part Number
ADC14DS105KARB/NOPB
Description
BOARD EVAL FOR ADC14DS105KARB
Manufacturer
National Semiconductor
Series
PowerWise®r
Specifications of ADC14DS105KARB/NOPB
Design Resources
ADC14DS105KARB Ref Design
Number Of Adc's
2
Number Of Bits
14
Sampling Rate (per Second)
105M
Data Interface
Serial
Inputs Per Adc
1 Differential
Power (typ) @ Conditions
1W @ 105MSPS
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
ADC14DS105
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADC14DS105KARB
www.national.com
ANALOG POWER
Exposed Pad
DIGITAL POWER
8, 16, 17, 58,
1, 4, 12, 15,
26, 40, 50
25, 39, 51
Pin No.
53
46
30
24
60
DLL_Lock
Symbol
DRGND
AGND
SDO
ORA
ORB
V
V
DR
A
Equivalent Circuit
6
Serial Data-Out: Serial data are shifted out of the device on this pin
while SCSb signal is asserted. This output is in TRI-STATE mode
when SCSb is deasserted.
Overrange. These CMOS outputs are asserted logic-high when
their respective channel’s data output is out-of-range in either high
or low direction.
DLL_Lock Output. When the internal DLL is locked to the input
CLK, this pin outputs a logic high. If the input CLK is changed
abruptly, the internal DLL may become unlocked and this pin will
output a logic low. Cycle Reset_DLL (pin 28) to re-lock the DLL to
the input CLK.
Positive analog supply pins. These pins should be connected to a
quiet source and be bypassed to AGND with 0.1 µF capacitors
located close to the power pins.
The ground return for the analog supply.
Positive driver supply pin for the output drivers. This pin should be
connected to a quiet voltage source and be bypassed to DRGND
with a 0.1 µF capacitor located close to the power pin.
The ground return for the digital output driver supply. This pins
should be connected to the system digital ground, but not be
connected in close proximity to the ADC's AGND pins.
Description