ADC14DS105KARB/NOPB National Semiconductor, ADC14DS105KARB/NOPB Datasheet - Page 4

• Manufacturer Part Number: ADC14DS105KARB/NOPB
• Description: BOARD EVAL FOR ADC14DS105KARB
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14DS105KARB/NOPB

• Design Resources: ADC14DS105KARB Ref Design
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 1W @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14DS105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14DS105KARB

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Pin No.
57
20
27
47
48
45
44
43
42
OUTCLK+
OUTCLK-
FRAME+
FRAME-
Symbol
PD_A
PD_B
TEST
WAM
DLC
Equivalent Circuit
4
This is a two-state input controlling Power Down.
PD = V
PD = AGND, Normal operation.
Note: This signal has no effect when SPI_EN is high and the SPI
interface is enabled. Thus, Power Down is not available when the
SPI Interface is enabled.
Test Mode. When this signal is asserted high, a fixed test pattern
(10100110001110 msb->lsb) is sourced at the data outputs
With this signal deasserted low, the device is in normal operation
mode. Note: This signal has no effect when SPI_EN is high and
the SPI interface is enabled.
Word Alignment Mode.
In single-lane mode this pin must be set to logic-0.
In dual-lane mode only, when this signal is at logic-0 the serial data
words are offset by half-word. With this signal at logic-1 the serial
data words are aligned with each other.
Note: This signal has no effect when SPI_EN is high and the SPI
interface is enabled.
Dual-Lane Configuration. The dual-lane mode is selected when
this signal is at logic-0. With this signal at logic-1, all data is sourced
on a single lane (SD1_x) for each channel. Note: This signal has
no effect when SPI_EN is high and the SPI interface is enabled.
Serial Clock. This pair of differential LVDS signals provides the
serial clock that is synchronous with the Serial Data outputs. A bit
of serial data is provided on each of the active serial data outputs
with each falling and rising edge of this clock. This differential
output is always enabled while the device is powered up. In power-
down mode this output is held in logic-low state. A 100-ohm
termination resistor must always be used between this pair of
signals at the far end of the transmission line.
Serial Data Frame. This pair of differential LVDS signals transitions
at the serial data word boundries. The SD1_A+/- and SD1_B+/-
output words always begin with the rising edge of the Frame signal.
The falling edge of the Frame signal defines the start of the serial
data word presented on the SD0_A+/- and SD0_B+/- signal pairs
in the Dual-Lane mode. This differential output is always enabled
while the device is powered up. In power-down mode this output is
held in logic-low state. A 100-ohm termination resistor must always
be used between this pair of signals at the far end of the
transmission line.
A
, Power Down is enabled and power dissipation is reduced.
Description