MAX1162EVKIT Maxim Integrated Products, MAX1162EVKIT Datasheet - Page 10

• Manufacturer Part Number: MAX1162EVKIT
• Description: EVAL KIT FOR MAX1162
• Manufacturer: Maxim Integrated Products

Specifications of MAX1162EVKIT

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ VREF
• Power (typ) @ Conditions: 12.5mW @ 200kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1162, MAX1062
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic high on CS places
the MAX1162 in shutdown (AutoShutdown) and places
DOUT in a high-impedance state. A logic low on CS
places the MAX1162 in the fully powered mode.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figures 6
and 7). Ensure that the duty cycle on SCLK is between
40% and 60% at 4.8MHz (the maximum clock frequen-
cy). For lower clock frequencies, ensure that the mini-
mum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz can
result in reduced accuracy due to leakage.
Note: Coupling between SCLK and the analog
inputs (AIN and REF) may result in an offset.
Variations in frequency, duty cycle, or other aspects
of the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence.
The analog input is stored in the capacitive DAC,
DOUT changes from high impedance to logic low, and
the ADC begins to convert after the sixth clock cycle.
SCLK drives the conversion process and shifts out the
conversion result on DOUT.
Figure 6. External Timing Diagram
10
______________________________________________________________________________________
DOUT
SCLK
t
DV
CS
t
CSS
Initialization after Power-Up and
1
t
ACQ
t
CH
Starting a Conversion
4
Digital Interface
t
CL
Timing and Control
6
t
DO
8
D15
D14
D13
D12
12
D11
Figure 5. Equivalent Input Circuit
SCLK begins shifting out the data (MSB first) after the
falling edge of the 8th SCLK pulse. Twenty-four falling
clock edges are needed to shift out the eight leading
zeros and 16 data bits. Extra clock pulses occurring
after the conversion result has been clocked out, and
prior to the rising edge of CS, produce trailing zeros at
DOUT and have no effect on the converter operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX1162 in
shutdown. For maximum throughput, force CS low
again to initiate the next conversion immediately after
the specified minimum time (t
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX1162 in shutdown.
C
SWITCH
AIN
D10
3pF
D9
TRACK
D8
16
HOLD
D7
GND
REF
D6
CAPACITIVE DAC
D5
C
DAC
D4
20
32pF
HOLD
D3
CSW
D2
).
TRACK
ZERO
R
800Ω
D1
IN
D0
24
t
CSH
AUTO-ZERO
t
RAIL
TR