MAX1162EVKIT Maxim Integrated Products, MAX1162EVKIT Datasheet - Page 13

• Manufacturer Part Number: MAX1162EVKIT
• Description: EVAL KIT FOR MAX1162
• Manufacturer: Maxim Integrated Products

Specifications of MAX1162EVKIT

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ VREF
• Power (typ) @ Conditions: 12.5mW @ 200kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1162, MAX1062
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3) Pull CS high at or after the 24th falling clock edge. If
4) With CS high, wait at least 50ns (t
Data can be output in three 8-bit sequences or continu-
ously. The bytes contain the results of the conversion
padded with eight leading zeros before the MSB. If the
serial clock has not been idled after the LSB (D0) and
CS has been kept low, DOUT sends trailing zeros.
Figure 10a. SPI Connections
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
format. Observe the SCLK to DOUT valid timing
characteristic. Clock data into the µP on SCLK’s ris-
ing edge.
CS remains low, trailing zeros are clocked out after
the least significant bit (D0 = LSB).
ing a new conversion by pulling CS low. A conver-
sion can be aborted by pulling CS high before the
conversion ends. Wait at least 50ns before starting a
new conversion.
*WHEN CS IS HIGH, DOUT = HIGH-Z
DOUT*
SCLK
CS
TIMING NOT TO SCALE.
SPI
MISO
SCK
I/O
SS
______________________________________________________________________________________
0
V
1
DD
0
16-Bit, +5V, 200ksps ADC with 10µA
0
CS
SCLK
DOUT
1ST BYTE READ
0
CSW
4
MAX1162
0
) before start-
D7
0
6
0
D6
0
D5
8
3RD BYTE READ
D4
20
When using the SPI (Figure 10a) or MICROWIRE
(Figure 10b) interfaces, set CPOL = 0 and CPHA = 0.
Conversion begins with a falling edge on CS (Figure
10c). Three consecutive 8-bit readings are necessary
to obtain the entire 16-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge. The
first 8-bit data stream contains all leading zeros. The
second 8-bit data stream contains the MSB through D8.
The third 8-bit data stream contains D7 through D0.
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1162 supports a maximum
f
nected to a QSPI master and Figure 11b shows the
associated interface timing.
Figure 10b. MICROWIRE Connections
SCLK
D3
of 4.8MHz. Figure 11a shows the MAX1162 con-
D2
MICROWIRE
MSB
D15
D1
SPI and MICROWIRE Interfaces
D14
I/O
SK
D0
LSB
SI
24
D13
HIGH-Z
2ND BYTE READ
D12
12
D11
Shutdown
D10
CS
SCLK
DOUT
QSPI Interface
D9
MAX1162
D8
16
D7
13