MAX1162EVKIT Maxim Integrated Products, MAX1162EVKIT Datasheet - Page 12

• Manufacturer Part Number: MAX1162EVKIT
• Description: EVAL KIT FOR MAX1162
• Manufacturer: Maxim Integrated Products

Specifications of MAX1162EVKIT

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ VREF
• Power (typ) @ Conditions: 12.5mW @ 200kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1162, MAX1062
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
quency band of interest. Minimize noise by presenting
a low impedance (at the frequencies contained in the
noise signal) at the inputs. This requires bypassing AIN
to AGND, or buffering the input with an amplifier that
has a small-signal bandwidth of several MHz, or prefer-
ably both. AIN has 4MHz (typ) of bandwidth.
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX1162’s
total harmonic distortion (THD = -102dB at 1kHz) at fre-
quencies of interest. If the chosen amplifier has insuffi-
cient common-mode rejection, which results in degraded
THD performance, use the inverting configuration (posi-
tive input grounded) to eliminate errors from this source.
Low temperature-coefficient, gain-setting resistors reduce
linearity errors caused by resistance changes due to self-
heating. To reduce linearity errors due to finite amplifier
gain, use amplifier circuits with sufficient loop gain at the
frequencies of interest.
12
______________________________________________________________________________________
CLK
CS
A0
A1
TIMING NOT TO SCALE.
IN1
IN2
IN3
IN4
4-TO-1
A0
MUX
A1
OUT
CONVERSION
Distortion
CHANGE MUX INPUT HERE
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1162’s offset (1mV (max) for +5V
supply), or whose offset can be trimmed while maintain-
ing stability over the required temperature range.
The MAX1162’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s ser-
ial interface as master, so that the CPU generates the
serial clock for the MAX1162. Select a clock frequency
between 100kHz and 4.8MHz:
1) Use a general-purpose I/O line on the CPU to pull
2) Activate SCLK for a minimum of 24 clock cycles.
CS low.
The serial data stream of eight leading zeros fol-
lowed by the MSB of the conversion result begins at
the falling edge of CS. DOUT transitions on SCLK’s
falling edge and the output is available in MSB-first
ACQUISITION
AIN
CS
MAX1162
Serial Interfaces
DC Accuracy