ISL6548A-6506EVAL1Z Intersil, ISL6548A-6506EVAL1Z Datasheet - Page 3

• Manufacturer Part Number: ISL6548A-6506EVAL1Z
• Description: EVALUATION BOARD ISL6548A-6506
• Manufacturer: Intersil

Specifications of ISL6548A-6506EVAL1Z

• Main Purpose: Special Purpose DC/DC, DDR Memory Supply
• Outputs And Type: 7, Non-Isolated
• Power - Output: 178W
• Voltage - Output: 1.8V, 3.3V, 5V, 1.5V, 1.2V, 2.5V, 0.9V
• Current - Output: 15A, 14A, 14A, 10A, 5A, 5A, 2A
• Voltage - Input: 3.3V, 5V, 12V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6506, ISL6548A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Switching: -

Active to Shutdown (S0 to S5 transition). Table 1 shows the
switch positions and the corresponding ACPI states.
If both the S3 and S5 switches are thrown to S3 and S5,
respectively, the board will default to an S5 state. If the board
is in either an S3 or S5 sleep state, the ATX supply is put into
standby mode, where only the 5VSBY rail is active.
Initial Power Up - Cold Start
If both the S3 and S5 switches are toggled to the ACTIVE
position prior to applying AC power to the ATX supply, the
board will immediately enter into S0 state when the 5VSBY
rail comes up after the AC power is applied to the ATX.
Figure 2 shows a Cold Start. Examination of the V
waveform shows this rail ramping up with the V
This is due to an external circuit that was included on the
evaluation board and is described in the section titled
“Grantsdale VDAC Sequencing Circuitry” on page 5.
S5 Sleep State to S0 State Transition
If the S5 switch is toggled to the S5 position prior to
application of AC power to the ATX supply, then the board
will immediately enter into the S5 sleep state when the
5VSBY rail comes up after the AC voltage is applied to the
ATX. The ISL6506 will bring up the 3VDUAL rail but all other
output rails will be inactive. The transition from the S5 state
to the S0 state will occur when the S5 switch is toggled to the
S3 SWITCH S5 SWITCH
5V/DIV
ACTIVE
ACTIVE
V
NOTE: ALL SIGNALS AT 1V/DIV UNLESS OTHERWISE STATED
S5
S3
S3
V
V
5V/DIV
TABLE 1. ISL6548A_6506EVAL1Z STATES
3VDUAL
5SBY
V
FIGURE 2. COLD/MECHANICAL START
S3
V
ACTIVE
ACTIVE
2V/DIV
VCC12
S5
S5
TIMEBASE: 10ms/DIV
V
V
V
V
DDQ_DDR
GMCH
TT_GMCH/CPU
TT_DDR
SLEEP STATE
V
S0 (Active)
5VDUAL
3
S3
S5
S5
V
DAC
ATX STATE
GMCH
Standby
Standby
Standby
Application Note 1285
DAC
ON
V
V
5V/DIV
VCC5
VIDPGD
rail.
ACTIVE position. Figure 3 shows this transition. Note that
the 3VDUAL rail are already active prior to the other rails soft
starting. If the ISL6506A had been used, the 5VDUAL rail
would have been active in the S5 state as well. During
testing of the evaluation board, it may be observed that the
5VDUAL rail stays up during the S5 sleep state. If this
behavior is observed, the explanation would be that the bulk
capacitor on the 5VDUAL rail did not discharge a significant
amount while the board was in the S5 sleep state.
S0 to S3 Sleep State Transition
Figure 4 shows the transition from the S0 state to the S3
sleep state.To achieve this transition, switch S3 is toggled to
the S3 position. When transitioning from the S0 state to the
S3 sleep state, it is important that the load on the
V
capable of supporting. If the load on V
excessive, V
DDQ_DDR
10V/DIV
NOTE: ALL SIGNALS AT 1V/DIV UNLESS OTHERWISE STATED
V
NOTE: ALL SIGNALS AT 500mV/DIV UNLESS OTHERWISE STATED
S3
V
V
10V/DIV
5V/DIV
VIDPGD
3VDUAL
V
FIGURE 3. S5 TO S0 STATE TRANSITION
FIGURE 4. S0 TO S3 STATE TRANSITION
V
DAC
rail be reduced to levels that the 5VDUAL rail is
S5
DDQ_DDR
V
V
V
V
DDQ_DDR
GMCH
TT_GMCH/CPU
TT_DDR
V
V
V
V
DDQ_DDR
GMCH
TT_GMCH/CPU
TT_DDR
V
V
2V/DIV
VCC5
TIMEBASE: 100ms/DIV
VCC12
TIMEBASE: 20ms/DIV
voltage will collapse.
5V/DIV
V
DDQ_DDR
V
5VDUAL
S3
5V/DIV
V
S5
January 15, 2007
V
is
V
5V/DIV
VIDPGD
DAC
AN1285.0