ISL6548A-6506EVAL1Z Intersil, ISL6548A-6506EVAL1Z Datasheet - Page 6

• Manufacturer Part Number: ISL6548A-6506EVAL1Z
• Description: EVALUATION BOARD ISL6548A-6506
• Manufacturer: Intersil

Specifications of ISL6548A-6506EVAL1Z

• Main Purpose: Special Purpose DC/DC, DDR Memory Supply
• Outputs And Type: 7, Non-Isolated
• Power - Output: 178W
• Voltage - Output: 1.8V, 3.3V, 5V, 1.5V, 1.2V, 2.5V, 0.9V
• Current - Output: 15A, 14A, 14A, 10A, 5A, 5A, 2A
• Voltage - Input: 3.3V, 5V, 12V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6506, ISL6548A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Switching: -

Evaluation Board Performance
This section presents the performance of the
ISL6548A_6506EVAL1Z evaluation board while subjected to
various conditions.
Switching Regulator Ripple Voltages
Figure 8 shows the ripple voltage on the V
outputs.
Transient Performance
Figures 9, 10, 11, 12, 13 and 14 show the response of the
outputs when subjected to a variety of transient loads while
in the Active (S0) State. Figure 9 shows V
transient loading. The response of the V
to the transient load brings the output voltage back into
regulation very quickly.
NOTE: ALL SIGNALS AT 50mV/DIV UNLESS OTHERWISE STATED
FIGURE 8. V
50mV/DIV AC COUPLED
FIGURE 9. TRANSIENT ON V
V
V
GMCH
TT_GMCH/CPU
V
DDQ_DDR
DDQ
V
GMCH
V
V
DAC
20mV/DIV AC COUPLED
TIMEBASE: 1µs/DIV
TT
TIMEBASE: 200μs/DIV
and V
(0.9V OFFSET)
(2.5V OFFSET)
V
(1.5V OFFSET)
10A/DIV
I
UGATE(GMCH)
(1.8V OFFSET)
LOAD
V
DDQ_DDR
10V/DIV
(1.2V OFFSET)
GMCH
6
RIPPLE VOLTAGE
DDQ_DDR
DDQ_DDR
DDQ
DDQ
V
UGATE(DDQ)
10V/DIV
and V
Application Note 1285
regulator
under
GMCH
Figure 10 shows V
causes V
While the load is being applied to the V
a noticeable reaction in the V
the V
load on the V
Figure 11 shows V
V
Again, the reaction of the V
loading on the V
V
where the V
V
rail did not appear to be affected as much as the V
rail. This is because a linear regulator (V
respond much faster than a switching regulator
(V
TT_DDR
DDQ_DDR
DDQ_DDR
DDQ_DDR
NOTE: ALL SIGNALS AT 50mV/DIV UNLESS OTHERWISE STATED
NOTE: ALL SIGNALS AT 50mV/DIV UNLESS OTHERWISE STATED
TT_DDR
FIGURE 10. SOURCING TRANSIENT ON V
FIGURE 11. SINKING TRANSIENT ON V
TT_DDR
to sink current.
TT_DDR
rail. In both cases, sourcing and sinking current,
rail has responded to the loading, the V
). This difference in response is because the
TT_DDR
rail is derived from the V
V
V
TT_DDR
TT_GMCH/CPU
V
TT_GMCH/CPU
V
to source current.
TT_DDR
TT_DDR
DDQ_DDR
DDQ_DDR
V
V
GMCH
V
rail has been loaded and the
TIMEBASE: 200µs/DIV
GMCH
V
TIMEBASE: 200µs/DIV
V
V
DAC
rail is seen by the V
DAC
TT
TT
(0.9V OFFSET)
(0.9V OFFSET)
rail is transferred directly to the
(2.5V OFFSET)
(1.5V OFFSET)
(2.5V OFFSET)
(1.5V OFFSET)
1A/DIV
I
1A/DIV
DDQ_DDR
(1.8V OFFSET)
I
under a transient that causes
(1.8V OFFSET)
under a transient loading that
LOAD
LOAD
(1.2V OFFSET)
DDQ_DDR
(1.2V OFFSET)
rail is evident since the
DDQ_DDR
TT_DDR
rail as well. Since
TT_DDR
DDQ_DDR
TT_DDR
TT_DDR
rail, there is
January 15, 2007
) will
rail, any
DDQ_DDR
TT_DDR
rail.
AN1285.0